Abstract: In a data processing multiprocessor system having distributed shared resources where each system processor (7) is provided with at least a local memory (8) to which it get access through a local bus (11), and with an interface unit (10) for connection of the local bus (11) to a system bus (5) and wherein each of the system processors may have access the local memory of another processor through its own local bus, its own interface unit, the system bus and the local bus of the other processor, deadlock is prevented by providing a bypass unit (40) of the interface unit (10) for enabling access from the system bus to the local bus through the bypass unit, a block (9) connected between the local bus and the interface unit (10) for latching system bus access requests received from an agent processor on the local bus, and a block (12) for isolation of the agent processor outputs from local bus, so that each agent processor may post read/write operations in the related latching block (9) for latching bus access requ

Abstract: Cache memory having pseudo virtual addressing, in which the addressing is performed by using the "offset" field of a current address and a physical address field of an address previously used and stored in a first register, and where, for each logical current address a comparison is made between the logical page addresses of the current address and that of the last used physical address which is stored in a second register. Along with the requested information the cache memory outputs, if available, the effective physical page address of the information, which is compared with the physical page address used for addressing and stored in the first register. In this way, the addressing is performed by physical addresses but without need to wait for translation of a virtual/logical address into a physical address.

Abstract: Memory system and related error detection and correction apparatus wherein the memory, independently on its parallelism, is organized in modules having single byte parallelism, each module having a section with a plurality of bit parallelism for storing SEC-DED codes related to the information stored in the module and wherein a fast memory, addressed with the information codes and the related SEC-DED codes read out from a memory module produces an information output code, corrected as a function of the SEC-DED code, a parity check bit for the corrected information code, and further bits indicative of a corrected single error and a multiple error which cannot be corrected.

Abstract: A multiprocessor system architecture in which two processors are each provided with an autonomous bus and the two buses can be selectively connected to each other to form a unique system bus which enables access by all processors to common memory resources connected to one of the autonomous buses. The communication between processors takes place through messages stored into mailboxes located in the common memory. The presence of a message is evidenced by a notify/interrupt signal generated by a logic unit to which each processor has access to modify and verify the logic unit's status, using the processor's autonomous bus, and without interfering with operations using the other autonomous buses of the other processor. Such verification and access does not require access to common memory resources nor polling operations to verify the status of messages stored into "mailboxes".

Abstract: Control circuit for a dot matrix printing head of the permanent magnetic type or simple electromagnet type, wherein a printing element is subjected to a variable magnetic flux, owing to an energization current and/or to a movable armature movement, which causes an energization current to be established in the printing element for its actuation. The energization current is switched off for the deactivation of the printing element and which thereafter establishes a shorting path letting a current, induced in the printing element by mangetic flux changes due to the movable armature movement, to flow in the printing element, with a damping effect on the armature movement.

Abstract: An armature group for mosaic printing head has a plurality of armatures wherein each armature which is part of an actuation electromagnet associated with one of a plurality of printing needles, is fixed to an elastic arm of a spring steel spider having as many arms as there are armatures. The spider, besides performing an armature positioning function allows the armature group to be handled as a unitary element which is easy to assemble. The thrust arm of each armature further has a double bend so that the plane between such arm and the corresponding needle head is perpendicular to the axis of the needle and passes through the fulcrum of the armature. This minimizes the buckling force which the needle has to undergo during the actuation phase. The construction of the armature group can be accomplished by a completely automated manufacturing process.