Abstract: A data processing system comprises a data processing unit coupled to a cache unit which couples to a main store. The cache unit includes a cache store organized into a plurality of levels, each for storing blocks of information in the form of data and instructions. The cache unit further includes an instruction buffer having first and second sections for storing instructions received from main store. Each instruction buffer section includes a plurality of word storage locations, each location having a number of bit positions. A predetermined bit position of each location is used to indicate when an instruction word has been written into the location. Control apparatus coupled to each of the buffer sections is operative to reset all of the word locations to binary ZEROS when a command requesting an instruction block from main store is ready to be transferred thereto. It is set to a binary ONE state when an instruction word is loaded into the location.

Abstract: A method and apparatus for assuring the accuracy of data received by any device in a computer system from any other device in the same computer system or from another computer system. The existing hardware of a computer system is utilized to generate a cyclic redundant check character each time a unit of data is transmitted. The cyclic redundant check character is concatenated to the right of such data transmitted. Each time that the particular data is received, the check character and the data with which it is associated, is again manipulated in the same manner as in generating the check character. If the data received is the same as the data transmitted, the result of such manipulation is zero.

Abstract: A data processing system having a control store storing firmware words for controlling the system, logic for executing logical operations on input data, including the performing of a first and second data processing routine, and apparatus for addressing the control store to access selected firmware words to control the execution of desired logical operations on the input data. The system operates in a particular mode of control to suspend the operation of the first routine in order to execute the second routine whereby the logical apparatus includes a register for saving a return address associated with the last instruction of the first routine. When the system terminates the second routine and restores the first routine to operation, the contents of the save register are employed, with the lowest order bit thereof inverted, to access the control store to fetch the firmware word used to reenter the first routine.

Abstract: An automatic cash depository having a tiltable feeding mechanism which receives an inserted deposit envelope and delivers it to a collection bin. Controls are provided for maintaining the feeding mechanism in a first position representing a blind feed path which does not present access to the collection bin. After the deposit envelope has fully entered the feeding mechanism and the insertion slot has been closed by a rotatable bolt closure, the control tilts the feeding mechanism and causes the envelope to be delivered to the collection bin.

Abstract: The performance of a scientific ADD instruction is improved by storing the mantissas of both operands in each of two random access memories, selecting the mantissa with the smaller exponent, shifting that mantissa and performing the ADD operation of adding the mantissas in one machine cycle.

Abstract: There is disclosed herein an apparatus for use in automated testing of elements in data processing systems such as the central processing unit. The system is comprised of a microprocessor with associated firmware, RAM and peripheral communications devices. There are two communication interface ports for receiving commands and instructions from local and remote computer terminals or from data processing units programmed to cause the testing apparatus to perform predetermined sequences of tests. There is also a port for connection to a portable maintenance panel which can be held in the hand of a field engineer for controlling the testing apparatus. The system is designed to replace prior art maintenance panels used for debugging computer hardware.

Abstract: A method of symptom compression involves a symptom compression device receiving binary coded information including bits signifying symptoms present in the course of each operating cycle at selected points in an integrated logical network, microprocessor or the like. The device includes a first register, a second shift register, an EXCLUSIVE OR logic network, and a display. The binary coded information is received on parallel inputs of the first register and applied from parallel outputs of the first register to a set of inputs of the EXCLUSIVE OR network, a second set of inputs which is connected to at least some parallel outputs from the second shift register. A set of outputs from the EXCLUSIVE OR network is connected to parallel inputs of the second shift register. In each cycle, the bits in the second shift register, which accumulate information representative of symptoms, are shifted in one direction and are recirculated. The display is connected to the parallel outputs from the second shift register.

Abstract: Mantissa results of floating point operations are truncated to words of 24 bits each by storing the 64 bit mantissa result in a first address location of a random access memory, and storing binary ZEROs in the 48 least significant bit positions of a second address location of the random access memory. The mantissa result is truncated by addressing the high order 24 bits at the first address location and the 48 binary ZEROs at the second address location.

Abstract: A memory subsystem includes at least one up to a number of memory module boards identical in layout and construction. The board includes a number of memory chips which are positioned in a number of physical row locations together providing a predetermined number of addressable contiguous memory locations corresponding to a predetermined increment of memory capacity. The board includes a set of switches whose input terminals are connected to receive predetermined ones of a plurality of address signals. These predetermined signals are coded specifying the segments of memory being accessed. The signals applied to the switch output terminals are logically combined and the resulting signal is applied to a group of memory present circuits connected to receive other ones of the address signals representative of the row of chips being addressed.

Abstract: An interrupt handling apparatus for a data processing system comprising a plurality of processing units and a working memory to which the units may access through a common bus by means of multilevel priority or access requests.Access requests are forwarded by each unit to a bus access controller preferably made part of the working memory through a single lead for each unit, irrespective of the access request priority level; and if the priority level of an access request is high, a high priority level access request signal is distributed by the high priority level interrupting unit to the other system units, which mask their possible access request of a lower priority level in response to such signal.The bus access controller grants access to a unit at a time on a priority basis determined by a priority network in the controller totally insensitive to any priority level difference of the access requests.

Abstract: A timing generator circuit includes a pair of multitap cascaded delay lines of like construction. Each delay line includes a plurality of sections each of which are constructed to provide the same increment of delay at each tap. A capacitive element connects between predetermined taps of the two delay lines to form a compensation network including a predetermined section of each delay line. The compensation network which operates to cancel out the effects of any mismatch resulting from connecting the delay lines in series.

Abstract: A solderable conductor pattern is formed on a ceramic substrate. The material of the conductor pattern is made by dispersing gold and certain inorganic binders in an inert liquid vehicle composition. Limited variations in the ranges of the amounts of the material in the composition particularly the range in the amount of copper oxide in the binder produce good adhesion of the pattern to fired substrates and simultaneously provide strong solder joints between leads of electronic devices soldered with a lead-indium solder to pads of a pattern of such material after the pattern has been fired on a substrate without the necessity for physically or chemically cleaning the pads. The binders of the material comprise certain amounts of the crystalline materials, copper in the form of its oxides CuO or Cu.sub.2 O, cadmium in the form of CdO, lead in the form of PbF.sub.2, and the balance being a glass which also contains lead and some cadmium.

Abstract: Partitioning, paging, and segmentation techniques are employed with virtual memory to provide more secure and efficient storage and transfer of information. The virtual memory is divided into a plurality of partitions with real memory storage provided by paging the plurality of partitions. User programs are segmented into logical units and stored in assigned partitions thereby isolating user programs and data. Unsegmented programs may be run by storage in a partition with direct addressing. Segment descriptors including partition, base, and bound are utilized in accessing memory. User domains are expandable by temporarily passing descriptor parameters from one routine to another with access flags limiting access thereto. By shrinking passed descriptors the receiving routine can be restricted to only a portion of the information defined by the descriptor.

Abstract: Multiple common buses are provided for coupling a plurality of units in a data processing system for the transfer of information therebetween. The central processing unit (CPU) allocates the multiple common buses to one of the units in response to bus requests received from various units desiring to use the common buses. Bus requests are generated in a synchronous manner by use of a timing signal originating in the CPU which is connected in series between the one or more units on each of the multiple common buses.

Abstract: In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of information, blocks of information may be transferred between main memory and an input/output controller (IOC) synchronously with operations of the central processor unit (CPU). Logic is provided for enabling one unit of the block of information to be transferred during a Data Multiplex Control (DMC) data transfer operation in which the requesting IOC requests a DMC data transfer of the CPU and provides the CPU with a channel number assigned to the requesting IOC. Means are provided within the CPU for determining: the direction of the data transfer, the address of the location of the unit of data to be transferred to/from the main memory, and the number of units of data remaining to be transferred between the main memory and the IOC.

Abstract: Digital data is recorded on the surface of a magnetic media such as a disk or diskette in the form of magnetic flux transitions identifying clock and data information in a modified frequency modulation (MFM) mode. A read head senses the flux transitions which are in turn converted to digital signals. A counter in the adapter starts to count when the adapter receives a digital signal. The count is transferred to a register and the counter presets when the adapter receives the next digital signal. The count is indicative of the time between the successive digital signals and should be representative of multiples of an integer. The count signals stored in the register address a read only memory whose output signals preset the counter to a value to compensate for the difference between the expected time and the actual time between the successive digital signals thereby reducing the read error rate.

Abstract: A switching regulator circuit for utilization with power supplies supplying a high DC output current including a plurality of control rectifiers and inductive reactors with sequential gating of the rectifiers at regular intervals for providing overlapped output current pulses from the reactors. An output circuit receives the rippled current comprised of the overlapped output current pulses for reducing the ripple therein. The output circuit includes a choke in series with the output which induces phase shift between the rippled current and the output current. A sensing winding associated with the choke eliminates the phase shift voltage for forming a feedback signal as an input to a control circuit. The control circuit utilizes the feedback signal to control the rate at which the rectifiers are gated sequentially.

Abstract: Apparatus for use in coupling an automated maintenance system of general utility to a central processing unit of a data processing system. The interface apparatus is comprised of path control and operational condition control registers to control and enable the paths accessed by the automated maintenance system and to control the conditions of operation of the central processing unit. A control point register stores control point information from the central processing unit indicating its internal status. This information is read and displayed by the automated maintenance system. Address and data registers serve to buffer data and addresses exchanged between the automated maintenance system and the CPU. The disclosed interface apparatus allows a general utility automated maintenance system to be adapted to test a specific central processing unit.

Abstract: A one's complement adder for adding two binary numbers A.sub.i, B.sub.i in the one's complement system is constructed from a conventional adder circuit by connecting the generate output signal G produced by the adder to the carry-in terminal of the adder. The value of the generate signal is independent of the signal applied to the carry-in terminal which prevents the adder from exhibiting sequential or indeterminate behavior.

Abstract: A solderable gold conductor composition is formed by dispersing gold and certain inorganic binders in an inert liquid vehicle composition which can be used to produce conductor patterns which patterns adhere to fired ceramic substrates and to which can be soldered leads of electronic components.A method of soldering a copper lead to a lead pad on a substrate. A conductor pattern including at least one lead pad is printed on the substrate using a gold thick film paste composition. The gold composition is composed of finely divided gold particles and finely divided inorganic binder particles dispersed in an inert liquid vehicle, containing by weight 98-99 percent gold particles and complementally 2-1 percent of inorganic binder particles. The binder consists essentially by total weight of gold and binder of 0.6-0.2 percent copper, 0.2 percent lead, 0.2 percent cadmium and the balance being glass.