Abstract: The presently claimed invention is to provide a package for compact RF signal system, and a method to form the package thereof in order to miniaturize the size of package, improve signal integrity, and reduce manufacturing cost. The package comprises a hybrid substrate with a sandwiched structure, in which the hybrid substrate comprises an upper layer and a lower layer with different dielectric properties being separated by an interposer for improving electrical isolation and mechanical stiffness. Metal layers are formed on the sidewalls of the opening to surround an active component, such that the metal sidewalls together with two ground plates in the upper and lower layers constitute a self-shielding enclosure inside the package to protect the active component.

Abstract: The presently claimed invention provides an electrochemical analytical apparatus and a method for evaluating performance of electroplating formulations of electrolyte solutions used for via filling. The electrochemical analytical apparatus comprises an electric power generating device, an electrical output signal measurement device, an electrochemical measurement device, and a motion generator. The electrochemical measurement device of the present invention comprises a supporting structure, a cavity, a cavity electrode, and a surface electrode. The electrical output signals of the cavity electrode and the surface electrode are measured during electroplating for calculating a filling performance value. The presently claimed invention provides an accurate, fast and cost effective method for evaluating performance of electroplating formulations, following with choosing the electroplating formulation of the highest FP value for actual microvia filling process.

Abstract: The present invention discloses a non-contact measurement system for measuring the three-dimensional (3D) shape of an object rapidly by using a unique light pattern and the implementation method thereof. The system comprises a pattern generation unit, a projection unit, a sensing unit and a processing unit. The pattern generation unit generates an enhanced color sequence according to predetermined rules. The sensing unit of the system comprises a hybrid sensor which can be operated in fast mode or precise mode. A dedicated decoding method for the present invention is also disclosed.

Abstract: An Amplitude-Shifted-Keyed (ASK) modulator/transmitter has fall time enhanced by pulsing pull-up and pull-down enhancement switches on for a short period of time after a data transition. The enhancement switches draw energy from a coupling capacitor to more rapidly reduce an amplitude of the carrier wave being output. An input carrier wave is applied to gates of p-channel and n-channel current sources that drive the coupling capacitor. Gates of the n-channel and p-channel enhancement switches also receive the input carrier wave when data is high, but are disabled when data is low. Multiple p-channel and n-channel transistors may be used in parallel for each current source or enhancement switch. Each of the multiple transistors in parallel has a gate that is AND'ed with an index signal. The index signals are programmable and determine how many of the parallel transistors are enabled, thus determining the aggregate current.

Abstract: A sine wave generator for a Direct Digital Synthesizer (DDS) converts a digital phase input into a digital sine wave output. Sine values and slopes are stored in read-only memory (ROM) for coarse upper phase bits in a first quadrant. A quadrant folder and phase splitter reflects and inverts values from the first quadrant to generate amplitudes for all four quadrants. Each sine value and slope is stored for a range of lower phase bits. A Delta bit separates upper and lower phase bits. Delta conditionally inverts the lower phase bits, the sine value, and the final polarity. A reduced AND logic array multiplies the slope by the conditionally inverted lower phase bits. A reconstructed ADD logic array then adds the conditionally inverted sine value. The conditionally inverted polarity is added to generate the final sine value. Sine generation logic is streamlined with conditional inversion based on the Delta bit.

Abstract: A computer implemented method for tracking a marker on a deformable surface in augmented reality (AR) applications, comprising: detecting image-key-points in a currently processed video frame of a video-captured scene; performing key-point-correspondence searching and matching the image-key-points with model-key-points are identified from an original image of the marker, comprising: calculating an key-point matching score for each image-key-point; applying a key-point matching score filter on the key-point matching scores; restricting the searching of the image-key-points in the currently processed video frame to within same mesh block determined in a previously processed video frame of the captured video frames; and applying adaptive thresholds on the key-point matching scores in determining successful matches of the image-key-points; performing motion detection of the marker in the video-captured scene and halting the application of the key-point matching score filter and suspending the restriction on the i

Abstract: An image processor generates a Super-Resolution (SR) frame by upscaling. A Human Visual Preference Model (HVPM) helps detect random texture regions, where visual artifacts and errors are tolerated to allow for more image details, and immaculate regions having flat areas, corners, or regular structures, where details may be sacrificed to prevent annoying visual artifacts that seem to stand out more. A regularity or isotropic measurement is generated for each input pixel. More regular and less anisotropic regions are mapped as immaculate regions. Higher weights for blurring, smoothing, or blending from a single frame source are assigned for immaculate regions to reduce the likelihood of generated artifacts. In the random texture regions, multiple frames are used as sources for blending, and sharpening is increased to enhance details, but more artifacts are likely. These artifacts are more easily tolerated by humans in the random texture regions than in the regular-structure immaculate regions.

Abstract: This invention discloses using one or more color-encoded fringe patterns for optically, three-dimensionally measuring an object's shape. In one embodiment, a color-encoded fringe pattern comprising a plurality of fringes that are modulated in intensity is configured as follows. An individual fringe selected from the fringes comprises a colored line at a location on the fringe width. The colored line has a line width that is substantially narrower than the fringe width in order that the colored line has a substantially similar intensity over the line width. The individual fringe excluding the colored line has a fringe color that is substantially uniform over the individual fringe. The fringe color is substantially different from the line color. Fringe colors of all the fringes are substantially similar, thereby enabling a major portion of the color-encoded fringe pattern to provide a substantially-uniform illumination color for projection onto the object.

Abstract: A transistor-based full-wave bridge rectifier is suitable for low A.C. input voltages such as received by a Radio-Frequency Identification (RFID) device. Voltage drops due to bridge diodes are avoided. Four p-channel transistors are arranged in a bridge across the A.C. inputs to produce an internal power voltage. A comparator receives the A.C. input and controls timing of voltage boost drivers that alternately drive gates of the four p-channel transistors with voltages boosted higher than the peak A.C. voltage. Four diode-connected transistors are connected in parallel with the four p-channel bridge transistors to conduct during initial start-up before the comparator and boost drivers operate. Substrates are connected to the power voltage on the power-voltage half of the bridge and to the A.C. inputs on the ground half of the bridge to fully shut off transistors, preventing reverse current flow. The transistor bridge can be integrated onto system chips.

Abstract: A computer implemented method of load shedding used in stream computing system that considers the relative importance of each of the applications processing the incoming input data or events. The method of load shedding method also accounts for system physical constraints, such as memories and CPU utilization. The load shedding method first observes the workload of each application and arriving rate of the incoming input data or events. If the system is under an overloading condition, calculate a input data or event drop ratio for each application such that the projected sum of all applications' workload will be at or below the system capacity when the unprocessed input data or events are dropped according to the drop ratio for each application.

Abstract: This invention discloses an encoding apparatus and a decoding apparatus for scalable video coding such that a non-scalable video decoder is usable for decoding a scalable video bit-stream comprising a base layer bit-stream and an enhancement layer bit-stream. In one embodiment, a source video frame is downscaled to give a downscaled video frame, which is then encoded into the base layer bit-stream. The difference between the source video frame and an up-scaled video frame reconstructed from the downscaled video frame in the base layer bit-stream yields a residual frame. The residual frame is partitioned into a number of residual sub-frames each having a resolution that is the downscaled video frame's resolution. The residual sub-frames are encoded into the enhancement layer bit-stream. Thereby, a non-scalable encoder is usable to encode both the downscaled video frame and the residual sub-frames, allowing both bit-streams to be decodable by employing only one non-scalable decoder.

Abstract: The presently claimed invention provides a method for stitching a plurality of images together in a way with least memory and CPU usage, and minimum file input and output, while still possessing fast computation speed to avoid post-scan delay for whole slide viewing and good stitching quality. The method of the present invention comprises the steps of calculating featureness of each candidate strip of a image by applying a mathematical transformation, calculating offset of the strip with correlation maximum location, calculating stitching reliability of the candidate strip from the pre-defined weighted function of its featureness and the correlation coefficients of each matching block, and determining optimal stitching path with stitching reliability.

Abstract: This invention discloses a lighting device for omnidirectional light emission with efficient heat dissipation. In one embodiment, a lighting device comprises lighting modules circumferentially arranged such that generation of the omnidirectional light is allowable, and a supporting unit attached to each lighting module's heat-dissipating side for providing mechanical support. A space formed by minimally enclosing all the lighting modules includes a first polar opening, a second polar opening opposite thereto, and a ventilation channel between the two polar openings for enabling air flowing through the ventilation channel to carry away at least part of heat obtained from the heat-dissipating sides of the lighting modules to outside said space. A line-of-sight path between the two polar openings is identifiable, allowing a direct flow of air that advances through the ventilation channel between the two polar openings to be realizable, thereby promoting the carrying away of heat to outside said space.

Abstract: The presently claimed invention provides a method for optimizing an electrodeposition process of a plurality of vias in a wafer. Instead of simulating a large number of via on the wafer for via filling, a representative via is selected with the maximum value of critical factor, which is a function of process parameters. The filling of the representative via is simulated with different sampling points to find out the filling goodness in order to find out the optimized process windows of process parameters. An optimizer is also disclosed, which either provides sampling points or reduces sampling points under artificial neural network method. Calculation of filling goodness is used for evaluating via filling quality and further comparing among via fillings simulated at different sampling points. Consequently, the method of present invention is able to shorten the simulation time for via filling as well as provide a process window with high accuracy.

Abstract: A system for bonding a die to a high power dielectric carrier such as a ceramic dielectric core with double-sided conductive layers is described. In the system, the upper conductive layer has a first area whose surface has a first wettability. A second area that at least partially surrounds the first area has a surface with a second wettability that is greater than the first wettability. During bonding, an adhesive material bonding a chip to the substrate spreads among the first area by a downward force placed on the chip. Due to the difference in wettability, the adhesive material then spreads among the second area by a wetting force generated by the greater second wettability of the second area surface causing the chip to be drawn down until reaching a predetermined position. The predetermined position can be determined by substrate protrusions or substrate cavities.

Abstract: A polarization beam splitter includes at least six prisms assembled together to form a single solid components. At least one diagonal interface is formed by a combination of two or more prism surfaces. The solid polarization beam splitter component has at least four light entrance/exit surfaces with at least one of the light entrance/exit surfaces including a step. At least one of the prisms has a non-triangular cross-sectional shape. At least one surface of a prism that forms a portion of the diagonal interface has a polarization beam splitting material disposed thereon resulting in a diagonal interface that includes a polarization beam splitting material. The polarization beam splitter can be incorporated into various image projection apparatus including 2D, multiple image, and 3D projection apparatuses.

Abstract: A computer processor implementable method of decoding low-density parity-check (LDPC) code, comprising: receiving a log-likelihood-ratio (LLR) input bitstream; performing a combined bit-deinterleaving and reordering process on the LLR input bitstream and storing in a physical memory space, comprising: determining a logical memory address for each LLR bit in the LLR input bitstream, determining a physical memory address for each LLR bit in the LLR input bitstream from logical memory address of the LLR bit; decoding the LLR input bitstream stored in the physical memory space; and performing a combined de-reordering and de-mapping process on the decoded LLR input bitstream.

Abstract: A Raman signal detection and analyzing system and a method thereof are disclosed. The Raman signal is generated by emitting an excitation light to a sample. The Raman signal is then modulated by passing through a plurality of optical filter and modulator. The resulting modulated Raman signal comprises two orthogonal components, which intensities are to be computed based on the first harmonic of said modulated Raman signal. The content of a specific analyte within the sample can then be determined based on the ratio of the intensities of the two components.

Abstract: This invention discloses a pulse-sensing device and methods for pulse sensing. In one embodiment, the device includes a robotic finger comprising a humanoid-finger structure, and an actuating-force transferring member for transferring an actuating force to the structure at an actuation point thereon and along an actuation direction. One end of the structure is pivotally mounted to a fulcrum and another end has a sensing area. The robotic finger is configured such that, when the sensing area contacts a person's wrist, a first perpendicular distance from the fulcrum to a first line is substantially longer than a second perpendicular distance from the fulcrum to a second line, where the first line is a straight line passing through a sensing point of the sensing area and being substantially perpendicular to the sensing area, and the second line is a straight line passing through the actuation point and orienting along the actuation direction.

Abstract: An on-chip temperature sensor circuit can be implemented in a standard complementary metal-oxide-semiconductor (CMOS) process using PNP transistors. A pair of transistors have collector currents that are sensitive to voltage, both directly and due to saturation currents. A scaling resistor connects to the emitter of one transistor and its voltage compared to the other transistor's emitter voltage by an error amplifier that generates a bias voltage to current sources that are proportional to absolute temperature since the saturation current sensitivity is subtracted out. The current is mirrored to sink current through a multiplier resistor from an output. An amplifier connected across the multiplier resistor compares a reference voltage to set the DC bias independent of temperature sensitivity. The temperature sensitivity is proportional to the ratio of the multiplier resistor and the scaling resistor, and is multiplied by a mirroring factor. A differential output may also be provided.