Abstract: A laser driver circuit compensates for non-linear behavior of Vertical-Cavity Surface-Emitting Laser (VCSEL) devices. A VCSEL has an internal parasitic capacitance that is charged while the VCSEL is on. When the VCSEL turns off, this internal parasitic capacitor discharges, keeping the VCSEL on longer, increasing the physical turn-off or fall time. The laser driver circuit compensates for the slower fall time by modulating both anode and cathode terminals of the VCSEL as the VCSEL is turned on and off. Both plates of the internal parasitic capacitor are discharged at turn off, cutting the parasitic discharge time in half. A cathode driver transistor modulates the cathode voltage while a source-follower transistor modulates the anode voltage. A modulating current may be switched using a current mirror structure. Multiple source-follower transistors may be selectable in parallel, with switches to select the total anode current, allowing for programmable compensation of the fall time.

Abstract: An electro-static-discharge (ESD) protection circuit has a vertical NPN transistor with a floating p-type base created by a deep p-type implant under an N+ source region. The deep p-type implant may be an ESD implant in a standard CMOS process. The p-type implant provides a low initial snap-back trigger voltage, but the holding voltage may be too low, creating latch-up problems. The holding voltage is raised by about one volt by connecting the emitter of the vertical NPN transistor to parallel resistor and diode paths. When the vertical NPN transistor is triggered, its current initially flows through the resistor, creating an increasing voltage drop through the resistor as current rises. Once the voltage across the resistor reaches 0.5 volt, the diode in parallel with the resistor becomes forward biased and shunts a higher current than the resistor, raising the holding voltage. A clamp transistor may replace the diode.

Abstract: A fly-back power converter has a current-estimating control loop that senses the primary output current in a transformer to control the secondary output. A primary-side control circuit switches primary current through the transformer on and off. A discharge time when a secondary current through an auxiliary winding of the transformer is flowing is generated by sampling a voltage divider on an auxiliary loop for a knee-point. A normalized duty cycle is calculated by multiplying the discharge time by a current that is proportional to the switching frequency and comparing to a sawtooth signal having the switching frequency. The peak of a primary-side voltage is sensed from the primary current loop and converted to a current and multiplied by the normalized duty cycle to generate an estimated current. An error amp compares the estimated current to a reference to adjust the oscillator frequency and peak current to control primary switching.

Abstract: An envelope detector receives an input that is an Amplitude-Modulated (AM) or Amplitude-Shift-Keying (ASK) coded signal. Each channel has a sample switch and a diode that charge an internal sampling capacitor. A hold switch connects the internal sampling capacitor to a summing output capacitor or to a post-processing circuit. A reset switch discharges the internal sampling capacitor after each sample. Two or more channels may be time multiplexed to sample alternate cycles of the input, and then their outputs combined by the summing output capacitor or by the post-processing circuit. The diodes may be reversed to detect the negative envelope rather than the positive envelope. Clocks for the switches may be generated from the input, or may be from a separate clock source. Since the sampling window is open for a whole input cycle, the clock source is insensitive to phase error.

Abstract: An electro-static-discharge (ESD) protection circuit is a power clamp between a high-voltage power supply VDDH and a ground. The power clamp protects high-voltage transistors in a first core and low-voltage transistors in a second core using a low-voltage clamp transistor. The low-voltage transistors have lower power-supply and snap-back voltages than the high-voltage transistors. Trigger circuits are triggered when an ESD pulse is detected on VDDH. One trigger circuit enables a gate of the low-voltage clamp transistor. A series of diodes connected between VDDH and a drain of the clamp transistor prevents latch up or snap-back during normal operation. During an ESD pulse, the series of diodes is briefly bypassed by a p-channel bypass transistor when a second trigger circuit activates an initial trigger transistor which pulses the gate of the p-channel bypass transistor low for a period of time set by an R-C network in the second trigger circuit.

Abstract: A charge/discharge protection circuit protects a battery from inadvertent shorting on a charger node that can connect to a charger or to a power supply of a portable electronic device. A single n-channel power transistor has a gate that controls a channel between the battery and the charger node. The gate is connected to the charger node by a gate-coupling transistor to turn off the power transistor, providing battery isolation. The gate is driven by a voltage-boosted clock through a switch activated by an enable signal. The enable signal also activates a grounding transistor to ground a gate of the gate-coupling transistor. A comparator compares voltages of the charger and battery nodes, and the compare output is latched to generate the enable signal. An inverse enable signal activates a second switch that drives the voltage-boosted clock to the gate of the gate-coupling transistor to turn off the power transistor.

Abstract: A two-stage op amp has a transconductance cell in a second stage modified to match a transconductance cell in a first stage. A transconductance swap network is inserted between transconductance cells and trans-impedance cells, such as current-steering networks, current mirrors, or drivers connected to the transconductance cells. The transconductance swap network directly connects the first transconductance cell to the first stage trans-impedance cell during a second clock phase, but crosses-over the first transconductance cell to the second-stage trans-impedance cell during a first clock phase. A first switched-capacitor network drives the gates of differential transistors in the first transconductance cell by alternately sampling an input and feedback, and equalizing to reset inputs. A second first switched-capacitor network drives differential transistors in the second transconductance cell, but during opposite clock phases.

Abstract: An equalized-impedance shadowed current cell can be arrayed in a Digital-to-Analog Converter (DAC) or other converters or applications. The Equalized-impedance shadowed current cell has primary differential transistors in parallel with shadow differential transistors that have gates driven inversely to gates of the primary differential transistors. A shadow current from the shadow differential transistors is much smaller than a primary current switched by the primary differential transistors. Cell current is not switched off to zero but to the shadow current. The ON state and OFF state impedances of the current cell may be matched during circuit design so that the impedance is the same regardless of digital input values. The Width and Length of the shadow differential transistors are adjusted so that overall output impedances for the ON and OFF states of the current cell are matched. Since output impedance is input code independent, high-speed performance is improved.

Abstract: A content distribution method with broadcast encryption, comprising: executing a setup process, comprising: generating public domain parameters, generating a server secret, and generating one or more client private keys, one for each content receiving client; executing an encryption process, comprising: generating a cipher text using the server secret, a subscriber set, and a randomness, the cipher text being constant and independent of total number of content receiving clients in a distribution network, generating a plain text using the server secret and the randomness, encrypting an original content into an encrypted content using the plain text; distributing the client private keys to the content receiving clients; distributing the cipher text to the content receiving clients; broadcasting the encrypted content through the distribution network; and executing a decryption process on the encrypted content by each of the content receiving clients in the distribution network.

Abstract: An analog-to-digital converter (ADC) has a chopper-stabilized sigma-delta modulator (SDM). The SDM uses switched-capacitor integrators to sample, hold, and integrate an analog input in response to non-overlapping multi-phase clocks. Chopper multipliers are inserted on the inputs and outputs of an op amp in a first stage integrator. The chopper multipliers swap or pass through differential inputs in response to non-overlapping chopper clocks. A master clock operating at a frequency of the multi-phase clocks is divided down to trigger generation of the chopper clocks. Delay lines ensure that the edges of the chopper clocks occur before the edges of the multi-phase clocks. The chopper multipliers have already switched and are thus stable when multi-phase clocks change so charge injection at switches controlled by the multi-phase clocks is not immediately modulated by chopper multipliers. This clock timing increases the time available to respond to charge injection at switches improving linearity.

Abstract: A Successive-Approximation Register Analog-to-Digital Converter (SAR-ADC) predicts compensation values for use in a future cycle. A compensation value is applied to capacitors in a calibration Y-side capacitor array to compensate for capacitance errors in a binary-weighted X-side capacitor array. Two compute engines pre-calculate predicted-0 and predicted-1 compensation values for a next bit to be converted. At the end of the current cycle when the comparator determines the current bit, the comparator also controls a mux to select one of the two predicted compensation values. Thus the compensation value is available at the beginning of the next bit's cycle, eliminating a long calculation delay. The compensation value for the first bit to be converted, such as the MSB, is calculated during calibration. Compensation values for other bits are data-dependent. Calibration values are accumulated during calibration to generate the first conversion compensation value for the first bit to be converted.

Abstract: A cascaded sigma-delta modulator has several modulator loops that have one or two sets of integrators, summers, and scalers, and a quantizer that generates a loop output. Input muxes to each loop select either an overall input or the loop output from a prior loop, allowing the modulator loops to be cascaded in series or to operate separately. Filter-configuring muxes after each modulator loop select either that loop's output or a loop output from any prior loop, or a zero. Each filter-configuring mux drives an input to a modified CIC filter. The modified CIC filter has an initial delay stage that receives the first filter-configuring mux output, and successive integrator stages that each receives a successive filter-configuring mux output. The modified CIC filter is a combination of a digital transform filter and a Cascaded-Integrator-Comb (CIC) filter. Modulator loops are powered down for lower-performance configurations or cascaded together for higher-performance configurations.

Abstract: A calibrating Analog-to-Digital Converter (ADC) has an X-side array with binary-weighted capacitors that connect to an X-side line and a Y-side array connected to a Y-side line. Each array has binary-weighted capacitors from a most-significant-bit (MSB) to a least-significant-bit (LSB), but the LSB capacitor is duplicated as a termination capacitor and a middle capacitor between upper and lower groups is also duplicated as a surrogate capacitor. During calibration, lower array capacitors are switched low while the upper capacitors are driven by a thermometer-code value on both X and Y arrays. The thermometer value is inverted to the X-array but remains uninverted on the Y array. The lower array bits are tested to final a calibration value that has X and Y side voltages balanced.

Abstract: A bandgap reference circuit has trimming-up resistors and trimming-down resistors for bi-directional trimming. PNP transistors have base and collectors grounded and emitters connected to parallel resistors. A difference resistor drives an inverting input of an op amp that drives a transistor that generates the bandgap reference voltage Vbg. A sensing resistor connects Vbg to a splitting node that connects to the non-inverting input through a first parallel resistor. The splitting node also connects through a second parallel resistor to the inverting input. Fuses or switches enable the trimming-up and trimming-down resistors. The trimming-up resistors are in series with the sensing resistor and the trimming-down resistors are in series with an output resistor that connects Vbg to reference voltage Vref. The circuit can be designed for a more typical process since bi-directional trimming allows Vref to be raised or lowered. Many circuits need no trimming when targeted for the typical process.

Abstract: A frequency dithering circuit reduces emissions that cause Electro-Magnetic Interference (EMI) by spreading the spectrum of a clock. The clock sequences a counter that drives a digital count value to a digital-to-analog converter (DAC). The DAC outputs a sawtooth wave with a wide voltage swing. A subtractor scales down the voltage swing to produce a reduced-swing sawtooth wave which is used as an upper limit voltage. Comparators trigger a set-reset latch to toggle the clock when current pumps charge and discharge a capacitor beyond voltage limits. Since the upper limit voltage is the reduced sawtooth wave from the subtractor, the amount of time to charge the capacitor varies, dithering the period of the clock. The degree of dithering can be adjusted by programming the feedback resistance in the subtractor. The subtractor reduces the sensitivity of dithering to errors in the DAC, allowing for an inexpensive, less precise DAC.

Abstract: A charge/discharge protection circuit protects a battery from inadvertent shorting on a charger node that can connect to a charger or to a power supply of a portable electronic device. A single n-channel power transistor has a gate that controls a channel between the battery and the charger node. The gate is connected to the charger node by a gate-coupling transistor to turn off the power transistor, providing battery isolation. The gate is driven by a voltage-boosted clock through a switch activated by an enable signal. The enable signal also activates a grounding transistor to ground a gate of the gate-coupling transistor. A comparator compares voltages of the charger and battery nodes, and the compare output is latched to generate the enable signal. An inverse enable signal activates a second switch that drives the voltage-boosted clock to the gate of the gate-coupling transistor to turn off the power transistor.

Abstract: There is described a hybrid bonding method for through-silicon-via based wafer stacking. Patterned adhesive layers are provided to join together adjacent wafers in the stack, while solder bonding is used to electrically connect the vias. The adhesive layers are patterned to enable outgassing and to provide stress relief.