Abstract: In various embodiments, an antenna array may comprise a dielectric; a first patch antenna disposed on a first region of the dielectric; a second patch antenna disposed on a second region of the dielectric; and a ground layer including a first sub-ground layer in contact with a lower portion of the first region of the dielectric, a third sub-ground layer in contact with a lower portion of the second region of the dielectric, and a second sub-ground layer spaced apart from a lower portion between the first region and the second region of the dielectric.

Abstract: A laminated glass antenna structure includes: a lower glass sheet including a first surface facing inside and a second surface at the upper end thereof; an upper glass sheet including a third surface adjacent to the lower glass sheet; an adhesive film positioned between the upper glass sheet and the lower glass sheet; and an antenna unit including a plurality of microstrip patch unit cells provided on the second surface and the third surface with respect to a ground plane provided on the first surface.

Abstract: The present disclosure provides a glass antenna structure including: a glass sheet provided in a vehicle; a monopole antenna unit located on one surface of the glass sheet; a plurality of rectangular patch planes located on another surface of the glass sheet at a position corresponding to the monopole antenna unit; and a co-planar waveguide (CPW) feeding line in contact with one end of the monopole antenna unit.

Abstract: A cam-type press apparatus includes a lower die, an upper die corresponding to the lower die and provided to be vertically movable, a cam base configured on a first die among the lower die and the upper die, at least one cam block provided on the cam base, a slide base configured on a second die among the lower die and the upper die, a cam slide in cam-contact with the cam base and slidably provided on the slide base, and a plurality of wear plates provided in contact with each other between the cam base and the cam slide and between the slide base and the cam slide, where at least one first pair of wear plates among the plurality of wear plates is in point-contact or line-contact with each other.

Abstract: The metal oxide nanoparticle includes a Zn-containing metal Me1 oxide nanoparticle of Zn1-xMe1xO (0?x?0.5) composition, and a metal Me2 ion surface treatment layer formed on a surface of the nanoparticle. Here, the metal Me1 is any one selected from Li, Be, Na, Mg, Al, K, Ca, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Ga, Ge, Rb, Sr, Zr, Nb, Mo, Ru, Rh, Pd, Ag, In, Sn, Sb, Ba and a combination thereof, and the metal Me2 is any one selected from Li, Be, Na, Mg, Al, K, Ca, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Zr, Nb, Mo, Ru, Rh, Pd, Ag, In, Sn, Sb, Ba and a combination thereof.

Abstract: Provided are a quantum dot, a method of preparing the quantum dot, an optical member including the quantum dot, and an electronic device including the quantum dot. The quantum dot includes a core including indium (In), A1, and A2; and a shell covering the core. A1 is a Group V element, A2 is a Group III element other than indium, and the core includes a first region, and a second region covering the first region. The first region does not include A2, and includes indium and A1, and the second region includes indium, A1, and A2, and indium and A2 are alloyed with each other in the second region.

Abstract: A battery voltage prediction apparatus may include: a state-of-charge (SOC) derivation unit configured to derive the SOC of a battery according to a current that is input or output to the battery and a capacity of the battery; a fixed parameter derivation unit configured to derive fixed parameters required for an equivalent circuit model based on voltages measured according to input/output currents of the battery and a time change within a preset time when the current is input or output for the preset time; and a tuning parameter derivation unit configured to derive at least one tuning parameter that varies depending on a time required for the equivalent circuit model when the current is input or output for a time exceeding the preset time.

Abstract: Disclosed is a method and system for providing a minimal aliasing error correction code. In constructing a single error correction (SEC) code by constructing a parity check matrix H for a data length k applied to a device, as the SEC code is designed to be valid and minimize generation of aliasing by checking some bits rather than all bits when nonzero binary column matrices different from each other are arranged in the parity check matrix, destruction of information can be prevented, and reliability of a device applying the SEC, such as DRAM or the like, can be improved.

Abstract: A vehicle includes a vehicle battery; a vehicle sensor configured to detect a current, a voltage and a temperature of the vehicle battery; and an alternator configured to output a target voltage to the vehicle battery. A controller is configured to calculate state of charge (SOC) estimation based on the current, voltage and temperature of the vehicle battery, calculate an initial SOC based on a direct current internal resistance (DCIR) map and apply the initial SOC to the SOC estimation, when an open circuit voltage (OCV) is maintained in a predetermined range after engine-off, and adjust an available SOC range based on a difference between an actual battery charge current amount, to which the initial SOC is applied, and the calculated SOC estimation.

Abstract: The disclosure relates to an array antenna, and specifically, relates to an array antenna which improves performance by using a shorting pin. The array antenna includes a first antenna, a second antenna, the first antenna and the second antenna sharing a ground, and a substrate disposed on an upper portion of the ground, and the second antenna is disposed in contact with an upper portion of the substrate, the first antenna is disposed by penetrating through centers of the substrate and the second antenna, the array antenna includes a plurality of feeding pins disposed by penetrating through the second antenna, the substrate, and the ground, and the array antenna includes a plurality of shorting pins penetrating through the second antenna, the substrate, and the ground to be symmetric with the plurality of feeding pins.

Abstract: A method for fabricating quantum dots according to the present disclosure includes (a) synthesizing InP cores based on an aminophosphine type phosphorus (P) precursor, (b) size-sorting the InP cores, and (c) forming at least two shells on the size-sorted InP cores. In this instance, the size-sorting includes precipitating the InP cores with an addition of a dispersive solvent and a nondispersive solvent to the InP cores and separating the InP cores using a centrifugal separator, wherein the InP cores are separated in a descending order by size by performing iteration with a gradual increase in an amount of the nondispersive solvent.

Abstract: A laminated glass antenna structure includes an upper glass located at the outermost position of a vehicle, a patch radiation unit located in at least a portion of the rear surface of the upper glass, and a lower glass located on the rear surface of the patch radiation unit. In particular, the patch radiation unit includes a strip line located in a height direction of the patch radiation unit, at least one extension line extending in the lateral direction of the strip line, and a patch element located at the end of the extension line.

Abstract: The disclosure relates to an array antenna, and more specifically, the array antenna configured by arranging a plurality of antenna elements at close positions. An array antenna is provided. The array antenna includes a first antenna operating in a first mode, and a second antenna operating in a second mode, wherein a correlation between an electric field of the first mode and an electric field of the second mode falls below a first threshold which is predetermined, or a correlation between a magnetic field of the first mode and a magnetic field of the second mode falls below a second threshold which is predetermined.

Abstract: Disclosed is a method and system for providing a minimal aliasing error correction code. In constructing a single error correction (SEC) code by constructing a parity check matrix H for a data length k applied to a device, as the SEC code is designed to be valid and minimize generation of aliasing by checking some bits rather than all bits when nonzero binary column matrices different from each other are arranged in the parity check matrix, destruction of information can be prevented, and reliability of a device applying the SEC, such as DRAM or the like, can be improved.

Abstract: The present disclosure relates to a technology for designing a transmitarray antenna based on the mode and incidence angle of feed radio waves. The transmitarray antenna according to one embodiment of the present disclosure includes a plurality of transmitting surface unit cells having different surface structures and different longitudinal lengths located in a plurality of regions, wherein the transmitting surface unit cells are arranged in a mixed manner in the regions based on the different longitudinal lengths and the phase of a transmission coefficient determined based on an input phase and an output phase based on the mode and incidence angle of radio waves transmitted from a feed antenna.

Abstract: The present disclosure provides II-VI based non-Cd visible light emitting quantum dots (QDs) and a manufacturing method thereof to solve the problems with broad full width at half maximum (FWHM) and low quantum efficiency. The present disclosure further provides a QD light emitting diode (QLED) using the II-VI based non-Cd visible light emitting QDs. The QDs according to the present disclosure include a II-VI based ternary ZnSeTe core, wherein a Se:Te ratio in the ZnSeTe core is 1:10 to 100:1. According to the present disclosure, it is possible to provide QDs that emit visible light ranging from red to blue by adjusting the Se:Te ratio in the II-VI based ternary ZnSeTe core.

Abstract: A method of verifying randomness of a bitstream is disclosed. The method includes receiving a bitstream consisting of n consecutive bits and dividing the bitstream into a plurality of bit blocks. In this case, n is a natural number of two or greater, each of the bit blocks consists of m consecutive bits, and m is a natural number of two or greater and is smaller than n. Further, the method includes allocating the plurality of bit blocks to a plurality of core groups in a graphics processing unit (GPU), processing the allocated bit blocks in the plurality of core groups in parallel, calculating random number level values of the allocated bit blocks, and determining whether the bitstream has randomness based on the calculated random number level values. Each of the core groups includes a plurality of cores capable of performing identical or similar tasks without separate synchronization.

Abstract: A protein memory cell and a protein memory system are provided. The protein memory cell includes: first and second electrodes disposed to be spaced apart from each other on a micro channel; a gap region defined between the first and second electrodes on the micro channel; an outer region defined as an opposite side to the gap region based on the first or second electrode on the micro channel; and a photosensitive protein changing conductivity between the first and second electrodes while moving between the gap region and the outer region depending on structural conversion of a chromophore.

Abstract: Provided are a quantum dot, a method of preparing the quantum dot, an optical member including the quantum dot, and an electronic device including the quantum dot. The quantum dot includes a core including indium (In), A1, and A2; and a shell covering the core. A1 is a Group V element, A2 is a Group III element other than indium, and the core includes a first region, and a second region covering the first region. The first region does not include A2, and includes indium and A1, and the second region includes indium, A1, and A2, and indium and A2 are alloyed with each other in the second region.