Abstract: Disclosed are a method, apparatus, electronic device, and storage medium. The method includes: determining a target undirected weighted graph corresponding to a target area from a start point to a target point, which includes a plurality of nodes, edges connected between the nodes, and cost weights respectively corresponding to the edges; performing a forward search from a start node corresponding to the start point and a reverse search from a target node corresponding to the target point based on the cost weights respectively corresponding to the edges of each node, to determine an initial encounter node for the forward and reverse searches; and determining a target shortest path from the start point to the target point based on the initial encounter node. Thus, exponential growth of expansion nodes in a middle part can be avoided, reducing spatiotemporal complexity of the search and improving efficiency of determining a shortest path.

Abstract: Disclosed are a fault diagnosis circuit, method and apparatus, and computer readable storage medium. The fault diagnosis circuit includes a safety protection circuit electrically connected to a protected circuit and a diagnosis module electrically connected to the safety protection circuit. The safety protection circuit is configured to perform check operation on stored data in the protected circuit to obtain first check data, perform error injection on second check data corresponding to the stored data, and generate a first check result signal based on the first check data and the second check data after the error injection. The diagnosis module is configured to diagnose faults in the safety protection circuit based on the first check result signal. From embodiments of this disclosure, the safety protection circuit is diagnosed faults through a simple hardware structure, to eliminate the faults based on a diagnosis result, thereby ensuring normal operation of a chip.

Abstract: Embodiments of the present disclosure disclose a method and apparatus for calculating tensor data based on a computer, a medium, and a device. The method includes: determining, from a second tensor, a dimension different from a dimension of a first tensor based on dimensions of the first tensor and dimensions of the second tensor; updating stride in the different dimension to a predetermined value; reading a to-be-operated data block of the second tensor from a buffer module based on updated stride with the predetermined value in each dimension of the second tensor, where the to-be-operated data block is a data block for which padding processing is performed; and performing binary operation on the first tensor based on the to-be-operated data block of the second tensor. According to the present disclosure, broadcasting may be conveniently achieved without difficulty of hardware design being increased.

Abstract: Disclosed are an integrated circuit and processing method for memory access, an electronic device, and a medium. The integrated circuit includes a first and second memory modules, and an access signal determining module respectively connected to the first and second memory modules. The access signal determining module includes: an interface circuit for transmitting a first memory access signal of a processor to the first memory module; an address filtering circuit for determining a target safety level corresponding to an access address of the first memory access signal; and an access signal processing circuit for offsetting the access address of the first memory access signal in response to the target safety level being a preset level, obtaining a second memory access signal based on the offset address, and transmitting the second memory access signal to the second memory module. Thus, a lower-safety-level memory can be accessed by a higher-safety-level function.

Abstract: Disclosed are a chip verification method and apparatus, an electronic device, and a storage medium. The method includes: obtaining data traffic mode information of a design under test of a chip in a target scenario; determining a data traffic feature corresponding to the design under test based on the data traffic mode information; constructing excitation corresponding to the design under test based on the data traffic feature; and verifying the design under test based on the excitation, to obtain a verification result of the design under test in the target scenario. According to the embodiments of this disclosure, a service scenario of the design under test can be replicated on a verification platform, so that effective verification can be performed on a work condition of the design under test in the service scenario, without constructing complex cases for scenario verification, thereby greatly improving effectiveness of scenario verification.

Abstract: Disclosed are a storage device and method, an electronic device, and a storage medium. The device includes: a first splitting logical module for splitting a first access command into at least two second access commands based on an access address of the first access command; and at least two storage array modules, each of which is configured to perform a corresponding access operation based on one of the at least two second access commands of the first splitting logical module. According to the embodiments, the first access command with relatively long burst is split into second access commands with smaller granularity, and the at least two storage array modules are parallel accessed, whereby the at least two storage array modules can respond in parallel, effectively reducing response time of the first access command and access time of each master when parallel access of masters exists, then improving access efficiency.

Abstract: Embodiments of the present disclosure disclose a circuit detection method and a data detection circuit. The circuit detection method comprises: if a current time point reaches a preset detection time period, based on a data storage address of a detected module, reading a data to be detected corresponding to the detected module from a storage area corresponding to the data storage address; using a preset calculation method corresponding to the detected module to perform a calculation on the data to be detected to obtain a first calculation result; based on the first calculation result and a preset calculation result corresponding to the data storage address, determining a fault state of the detected module. The embodiments of the present disclosure can detect the storage circuit in a timely and accurate manner without data verification by adding hardware, thereby saving space occupied by the system and reducing power consumption.

Abstract: The present disclosure provides a chip fault diagnosis method, which includes: determining an interrupt flag of an interrupt flag register based on first data identifying an interrupt state in the interrupt flag register; and determining a fault state of chip interrupt corresponding to the interrupt flag based on the interrupt flag. By adopting the technical solution provided by the present disclosure, a fault of the interrupt can be diagnosed in time, and the interrupt can be processed in time.

Abstract: Disclosed are a method and apparatus for controlling a hardware module, electronic device and storage medium. In an embodiment of the present disclosure, the method may include: timing a waiting state of the hardware module to obtain a current waiting duration of the hardware module when it enters a first waiting state; generating an interrupt signal based on the current waiting duration; determining program information corresponding to the current waiting duration under triggering from the interrupt signal; executing an action corresponding to the program information for the hardware module, and controlling it to enter a second waiting state. In the present disclosure, the hardware module is controlled to execute actions corresponding to different programs based on different waiting durations through an interrupt mechanism, thus controlling the hardware module to switch between waiting states with different power consumption, and achieving a good balance between energy saving and performance.

Abstract: The present application discloses a neural network computation method includes determining the size of the first feature map obtained when the processor computes the present layer of the neural network before performing convolution computation on the next layer of the neural network; determining a convolution computation order of the next layer according to the size of the first feature map and the size of the second feature map for a convolution supported by the next layer; performing convolution computation instructions from the next layer based on the convolution computation order. Exemplary embodiments in the present disclosure decrease the interlayer feature map data access overhead and reduce the idle time of a computation unit by leaving out the storage of the first feature map and the loading process of the second feature map.

Abstract: A processor detection method and device and a computer-readable storage medium are disclosed. The method comprises: determining a parameter stored in a first-type register in a detected processor, wherein the parameter stored in the first-type register relates to data need to be processed currently by the detected processor; based on the parameter stored in the first-type register, determining a working state of the detected processor. Embodiments of the present disclosure can conveniently and reliably realize the detection of interrupt loss, thereby effectively monitoring the situation of interrupt loss.

Abstract: Embodiments of the present disclosure disclose a circuit detection method and a data detection circuit. The circuit detection method comprises: if a current time point reaches a preset detection time period, based on a data storage address of a detected module, reading a data to be detected corresponding to the detected module from a storage area corresponding to the data storage address; using a preset calculation method corresponding to the detected module to perform a calculation on the data to be detected to obtain a first calculation result; based on the first calculation result and a preset calculation result corresponding to the data storage address, determining a fault state of the detected module. The embodiments of the present disclosure can detect the storage circuit in a timely and accurate manner without data verification by adding hardware, thereby saving space occupied by the system and reducing power consumption.

Abstract: Disclosed are a method and apparatus for controlling a hardware module, electronic device and storage medium. In an embodiment of the present disclosure, the method may include: timing a waiting state of the hardware module to obtain a current waiting duration of the hardware module when it enters a first waiting state; generating an interrupt signal based on the current waiting duration; determining program information corresponding to the current waiting duration under triggering from the interrupt signal; executing an action corresponding to the program information for the hardware module, and controlling it to enter a second waiting state. In the present disclosure, the hardware module is controlled to execute actions corresponding to different programs based on different waiting durations through an interrupt mechanism, thus controlling the hardware module to switch between waiting states with different power consumption, and achieving a good balance between energy saving and performance.