Patents Assigned to HOY TECHNOLOGIES CO
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Patent number: 8744796Abstract: The present invention discloses an algorithm integrating system and an integrating method thereof. The algorithm integrating system comprises a receiving module, an analyzing module, and a processing module. The receiving module receives at least one test algorithm. The analyzing module is connected to the receiving module and analyzes the at least one test algorithm to obtain at least one basic element from the at least one test algorithm. The processing module is connected to the analyzing module and screen out the at least one non-duplicate basic element based on the at least one basic element. Then, the processing module integrates the at least one non-duplicate basic element and generates a testing module.Type: GrantFiled: April 18, 2011Date of Patent: June 3, 2014Assignee: HOY Technologies Co., Ltd.Inventors: Chun-Chia Chen, Li-Ming Teng, Yu-Tsao Hsing
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Patent number: 8281199Abstract: A hybrid self-test circuit structure comprises a plurality of input terminals and a plurality of output terminals for testing a plurality of memory units. The circuit structure comprises a first level functional unit for driving a plurality of first output terminals electrically coupled to the first level functional unit to output an output signal according to an external control signal transmitted from the outside; a plurality of second level functional units for receiving the output signal and generating a test signal according to the output signal and outputting the test signal to the memory units; a parallel interface parallelly installed between the first level functional unit and at least one of the second level functional units; and a serial interface serially installed between the first level functional unit and at least one of the second level functional units.Type: GrantFiled: May 3, 2010Date of Patent: October 2, 2012Assignee: Hoy Technologies, Co., Ltd.Inventors: Yu-Tsao Hsing, Li-Ming Teng
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Publication number: 20120124441Abstract: The present invention discloses an embedded testing module and testing method thereof which encodes one or more test commands to reduce the storage space required by a testing memory. In addition, most functions of automatic test equipment can be replaced by the present invention, in which, through the testing memory according to the present invention, if errors are found during testing, the error information will be transmitted to the external automatic test equipment and the error information can be optionally recorded in a memory. A test operator can get detailed descriptions from the error information stored in the memory, so the test operator can save time for subsequent debugging and tracking operations concerning the errors.Type: ApplicationFiled: January 5, 2011Publication date: May 17, 2012Applicant: HOY TECHNOLOGIES COInventors: LI-MING TENG, YU-TSAO HSING
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Publication number: 20120089360Abstract: The present invention discloses an algorithm integrating system and an integrating method thereof. The algorithm integrating system comprises a receiving module, an analyzing module, and a processing module. The receiving module receives at least one test algorithm. The analyzing module is connected to the receiving module and analyzes the at least one test algorithm to obtain at least one basic element from the at least one test algorithm. The processing module is connected to the analyzing module and screen out the at least one non-duplicate basic element based on the at least one basic element. Then, the processing module integrates the at least one non-duplicate basic element and generates a testing module.Type: ApplicationFiled: April 18, 2011Publication date: April 12, 2012Applicant: HOY TECHNOLOGIES CO, LTD.Inventors: Chun-Chia Chen, Li-Ming Teng, Yu-Tsao Hsing
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Publication number: 20110267071Abstract: A hybrid self-test circuit structure comprises a plurality of input terminals and a plurality of output terminals for testing a plurality of memory units. The circuit structure comprises a first level functional unit for driving a plurality of first output terminals electrically coupled to the first level functional unit to output an output signal according to an external control signal transmitted from the outside; a plurality of second level functional units for receiving the output signal and generating a test signal according to the output signal and outputting the test signal to the memory units; a parallel interface parallelly installed between the first level functional unit and at least one of the second level functional units; and a serial interface serially installed between the first level functional unit and at least one of the second level functional units.Type: ApplicationFiled: May 3, 2010Publication date: November 3, 2011Applicant: HOY TECHNOLOGIES CO., LTD.Inventors: Yu-Tsao Hsing, Li-Ming Teng