Abstract: A system includes a memory to store an input data, an accelerator circuit comprising an input command execution circuit, a neuron matrix command execution circuit, and an output command execution circuit, and a processor, communicatively coupled to the memory and the accelerator circuit, to generate a stream of instructions from a source code targeted the accelerator circuit, each one of the stream of instructions comprising at least one of an input command, a neuron matrix command, or an output command, and issue the stream of instructions to the accelerator circuit for execution by the input command execution circuit, the neuron matrix command execution circuit, and the output command execution circuit.

Abstract: An accelerator circuit includes a control interface to receive a stream of instructions, a first memory to store an input data, and an engine circuit. The engine circuit includes a dispatch circuit to decode an instruction of the stream of instructions into a plurality of commands and a plurality of queue circuits. Each of the plurality of queue circuits supports a queue data structure to store a respective one of the plurality of commands decoded from the instruction, and a plurality of command execution circuits. Each of the plurality of command execution circuits is to receive and execute a command extracted from a corresponding one of the plurality of queues.

Abstract: An accelerator circuit including a control interface to receive a stream of instructions, a first memory to store an input data, and an engine circuit including a dispatch circuit to decode an instruction of the stream of instructions into a plurality of commands, a plurality of queue circuits, each of the plurality of queue circuits supporting a queue data structure to store a respective one of the plurality of commands decoded from the instruction, and a plurality of command execution circuits, each of the plurality of command execution circuits to receive and execute a command extracted from a corresponding one of the plurality of queues.

Abstract: A system includes a memory to store an input data, an accelerator circuit comprising an input command execution circuit, a neuron matrix command execution circuit, and an output command execution circuit, and a processor, communicatively coupled to the memory and the accelerator circuit, to generate a stream of instructions from a source code targeted the accelerator circuit, each one of the stream of instructions comprising at least one of an input command, a neuron matrix command, or an output command, and issue the stream of instructions to the accelerator circuit for execution by the input command execution circuit, the neuron matrix command execution circuit, and the output command execution circuit.

Abstract: An address fine-tuning acceleration system in the technical field of address fine-tuning is disclosed. The system includes a scheduling unit, a high-order physical register block, a shared mapping unit, an address checking unit, a low-order physical register block, an immediate value detection unit, a physical memory address fine-tuning detector, a new address generation unit, a reservation station, an execution and virtual-physical memory address conversion unit, and a submission unit.

Abstract: A method for implementing of a quick-release Variable Length Vector (VLV) memory access array in the technical field of software programs, which includes the following steps: Step 1: when a pipeline restarts to refresh an out-of-order queue each time, and the number of sending an entry recorded in a sending counter of the entry is equal to the number of returning the entry recorded in a returning counter of the entry, an ID of the entry is kept unchanged, and the ID is used for a next pushed request; Step 2: when the pipeline restarts to refresh the out-of-order queue each time, the number of sending the entry recorded in the sending counter is not equal to the number of returning the entry recorded in the returning counter and mirror resources are not exhausted, the existing entry is released, the ID, the sending counter and the returning counter of the entry are copied to another structure, and N IDs, each of which is in a non-busy status are selected from a free list, and a busy bit of each of the N IDs is