Abstract: A plurality of fatigue life test strips (16, 18, 20, 22) has each of the strips anchored to a base (12) which is subject to thermal cycling and consequent dimensional change which causes fatigue. The base is, at best, semiconductive, and the strips are conductive. The conductivity of each of the strips is measured by test circuit (52) so that, when one fails due to fatiguing, the failure is signaled.

Abstract: A digital signal processing system (100) removes DC bias in the output of a pyroelectric detector and similar types of detectors by adding together a first output signal which is inverted and a second output signal which is not inverted. The system (100) also removes offsets in the detector signal introduced by electronic circuits (readouts, amplifiers, drivers, etc.) between the detector and the system (100).

Abstract: A monolithic microwave integrated circuit is formed by positioning a distributed, transmission-line network over a microwave-device structure. The ground plane of the transmission-line network adjoins an interconnect system of the microwave-device structure and signal lines of the transmission-line network are adapted to communicate with the microwave-device structure through orifices of the ground plane. The invention facilitates the use of low-cost silicon-based transistors in monolithic microwave integrated circuits.

Abstract: A method for compensating for lateral distortion in a moving linear array using a frequency domain beamformer, comprising the steps of measuring the instantaneous lateral distortion of the linear array at discrete points along the array, corresponding to array element locations, calculating a shading weight for each of the discrete points along the array, corresponding to array element locations based on the instantaneous lateral distortion at each said point and calculating the compensated beam magnitude by multiplying said shading weight into the frequency domain beamformer equation.

Abstract: A polysilicon gate (42) of an N-channel MOSFET (40) includes a P+ doped central portion (42a), and N+ doped lateral portions (42b,42c) which face an N-type source (24c) and drain (26c) respectively. An N-type dopant is implanted into the surface portion of a P-type channel region (18) to reduce the surface doping and adjust the transistor threshold voltage to approximately 0.8 volts. The lowered channel doping reduces the electric field at the drain (26c) and suppresses injection of hot electrons from the drain (26c) into the gate oxide (14), and also reduces the electric field across the gate oxide (14) and suppresses charging thereof by hot electrons.

Abstract: A solid state triode employs the Hall effect to asymmetrically proportion flow of current through different branches of a number of cascaded bifurcated N- charge carrier channels (10,18,20), thereby providing an indication of strength and direction of an applied magnetic field by measuring magnitude and sense of the difference between currents flowing in the two channel branches (14,16,24,26,30,32). The solid state triode is formed on an silicon-on-insulator (SOI) substrate (47,48,49) in which an N+ source region (54) and at least two end N+ drain regions (56,58) are interconnected by an N- charge carrier channel (60) that is defined by a plurality of P+ regions (64a,64b,64c,64d) in a thin single crystal silicon substrate (49) between the source and drain regions (54,56,58). A polysilicon gate (52) overlies the N- channel and acts as a self-aligning mask during manufacture of the triode to precisely align the N+ and P+ doping to the polysilicon gate configuration.

Abstract: Boundary scan cells including mask circuitry having a mask latch for storing a mask flag that is serially scanned into the cell via a scan flip-flop. In a boundary scan cell having an output function, control circuitry responsive to the mask flag forces or holds the output of the cell at a state determined by one or more values scanned into the cell via the scan flip-flop if the mask flag is of a predetermined state that indicates the cell is masked. In a boundary scan cell having an input function, control circuitry responsive to the mask flag connects the output of the scan flip-flop to the input of the scan flip-flop if the mask flag is of a predetermined state that indicates the cell is masked.

Abstract: A method of estimating the directions of radiating sources (56, 58, 60) with respect to an array (46) of a number of antenna elements (48), each of which elements has a separate gain/phase control (50). With nominal gain and phase selected a first estimte of the radiating sources directions (.theta.) is accompished by application of the MUSIC algorithm (2). The algorithm is iteratively applied to a microprocessor (54) using updated gain and phase values. Iteration is terminated at that iteration which produces the maximum difference values of the smallest eigenvalue pair of Q.sub.(i).

Abstract: Multiple radio frequency (RF) outlet ports are provided along the side of a slow wave tube to establish a distributed RF output in response to the transmission of an e.sup.- beam through the tube. The tube has a periodically rippled inner surface, and the outlet ports are spaced along the tube by substantially integral numbers of ripple periods. When implemented as a backward wave oscillator, RF power is extracted during a single pass through the tube; a travelling wave tube amplifier implementation is also possible. The separation of the RF extraction from the absorption of the e.sup.- beam at the end of the tube eliminates RF reflections and permits water cooling of the e.sup.- beam absorber. The RF extraction ports are also preferably configured as built-in mode converters from a TM.sub.01 cylindrical tube mode to a TE.sub.10 rectangular extraction mode, with four symmetrically arranged rectangular extraction waveguides at each extraction location combining their energies into a single TE.sub.10 output.

Abstract: An electroluminescent display and method of fabricating the same is described in which an active driver panel (14) is integrated with a processed display panel (12) using a unique application of semiconductor wafer technology. A microelectronic driver circuit (32) and back electrode (34) are fabricated on a semiconductor wafer (30) to provide a panel for driving the display. Multiple driver circuits (32) and respective back electrodes (34) may be arranged on the wafer to form an active-matrix electroluminescent display. The display panel (12) includes a front electrode (18) and an adjacent phosphor panel (20) for illuminating the display. The driver panel (14) is adhered to the display panel (12) using either an indium bump connection or a thermal bond, which provide both mechanical and electrical coupling between the back electrodes (34) and the phosphor panel (20). Exposure of the active devices on the driver panel to destructive high processing temperatures inherent in display panel processing is avoided.

Abstract: A method and apparatus (30) for compensating for optical aberration created by a conformal window (60). The apparatus (30) comprises a one-dimensional corrector plate (32) for providing a varying amount of linear coma, first and second cylindrical lenses (34, 38) for providing a varying amount of astigmatism and a system for adjusting the corrector plate (32) and the lenses (34) and (38) to minimize the optical aberration created by the conformal window. The apparatus (30) of the present invention provides for correction of considerable amounts of optical aberration over a wide field of regard. The apparatus is simple in design, easy to install and cost effective.

Abstract: In a parallel processing architecture following the Single Instruction stream Multiple Data stream execution paradigm where a controller element is connected to at least one processing element with a local memory having a local memory address shift register adapted to receive and retain therein a globally broadcast memory base register address value received from the controller element for use by the processing element for access and transfer of data between the processing element and its respective local memory, a computer architecture for implementing indirect addressing and look-up tables includes a processing element shift register associated with the at least one processing element and adapted to receive and retain therein a local memory offset address value calculated or loaded by the associated processing element in accord with a first predetermined set of instructions.

Abstract: Electronic interconnection of two printed wiring structures. Two printed wiring boards or a flexprint circuit and a printed wiring board are interconnected by creating a plated hole pattern on a surface of the printed wiring board, and wherein holes of the pattern have a concave cross section. The holes of the plated hole pattern are mated with corresponding bumps or dimples disposed on the second printed wiring board or the flexprint circuit. The holes formed in the first printed wiring board are disposed a predetermined depth below a surface of the printed wiring board, typically to a depth of between 0.007 inches and 0.020 inches below the surface. The plurality of plated holes are formed by electroless plating or electroplating of the holes. The present interconnection structure provides for reliable and self aligning interconnection of the two printed wiring boards or the flexprint circuit and printed wiring board.

Abstract: A method and apparatus for protecting metal bumped chips during processing and for providing mechanical support to interconnected chips. A protective adhesive stop is affixed to a metal bumped chip so that the height of the stop is at least as high as the metal bump. The stop protects the metal bump during routine handling. When the chip is interconnected to another bumped chip by cold welding their respective metal bumps, the stop contacts the face of the second chip and provides mechanical support. The stop is preferably a thermoplastic that is heated to adhere it to the second chip. The addition of the protective stop facilitates automated processing of metal bumped chips, and provides stronger, faster, and lower power chips.

Abstract: A method for fabricating a super self-aligned bipolar junction transistor which reduces or eliminates emitter defects caused during critical etching steps by providing a non-critically thick dielectric etch stop (protection) layer (116) during all potentially damaging etching steps. An oxide or other dielectric layer (116, 130), is provided above the emitter region (152) of the semiconductor surface (110) during potentially damaging etching steps, such as dry etch procedures used to form critical device structures such as emitter opening 124 and sidewall spacers 146. Non-damaging etching procedures, such as wet etching, are used to remove dielectric protection layers (116, 130) to form less critical device structures, and/or form intermediate layer openings without damaging the silicon surface in the emitter (152), or other critical regions.

Abstract: Plasma wave tubes are disclosed having waveguide injection systems configured for injection of an RF signal to prebunch the electron beam of the tube and thereby control the frequency of an RF output signal. Preferred embodiments of the injection system include a plurality of rectangular waveguides arranged radially about a cylindrical waveguide member and joined to it for communication with its interior. Plasma wave tubes (140) are also disclosed that utilize the injection system as a collector (44C) to couple an RF output signal from the tube.

Abstract: A rugate filter (10) having suppressed harmonics includes a layer (18) of material disposed on a surface (14) of an optical substrate (12) having an index of refraction versus thickness profile that is the superposition of a principle sinusoid and a secondary sinusoid. The secondary sinusoid being superimposed about -90 degrees out of phase with the principle sinusoid.

Abstract: A predistortion linearizer (10) and method for distorting an AC input signal (42) to a power amplifier (24) provide a distortion to the input signal which is complementary to a distortion, in terms of gain and phase, introduced by the power amplifier as a function of signal amplitude, thereby to linearize the power amplifier. The linearizer includes a switching circuit (26, Z.sub.1 28, Z.sub.2) having an input terminal (16) and an output terminal (20) and a pair of antiparallel diodes (26, 28) connected between the input terminal and the output terminal of the switching circuit. The linearizer has also an impedance circuit (Z.sub.3) comprising solely passive electrical elements connected between the input terminal and the output terminal of the switching circuit, wherein elements of the impedance circuit have values selected to introduce the complementary distortion to the input signal as a function of amplitude of the input signal to linearize the power amplifier.

Abstract: A minimum phase shift microwave attenuator circuit, providing very low insertion phase change with changing attenuation levels. Three PIN diodes are biased in parallel from a common node. The PIN diodes are held at zero or reverse bias for the "no attenuation" state, and are made slightly lossy to produce the attenuation state. In the attenuation state, the PIN diodes are utilized as current controlled lossy capacitors which change resistance with applied bias, but maintain constant capacitance, thereby providing low insertion phase deviation across wide attenuation levels.

Abstract: A system is described which integrates terminal traffic in a digital voice cellular radio communication system. Data is conveyed from remote data stations and remote radio telephone stations over a reverse channel TDMA frame. The allocation of time slots in the reverse channel TDMA frame is controlled at the base station. The base station provides priority to radio telephones having digitized voice traffic. The base station assigns time slots within the reverse channel TDMA frame based upon allocation requests received from radio telephone stations and remote data stations. Remote data stations may contend on a random access for a minority of a set of time slots in the reverse channel data frame. Additionally, they may request an assigned slot by inserting an allocation request in a control slot of the reverse channel data frame. The base station allocates time slots on a voice radio telephone priority, and assigns any excess time slots to data stations waiting for access to the reverse channel.