Abstract: A counter includes an array of memory cells arranged in groups of memory cells, each group designating a counting decade, wherein each group of memory cells includes first and second word strings, each capable of storing a data word, and a fault flag, capable of indicating which word string contains the data word; sensing means coupled to the memory array for checking the status of the memory cells and for generating fault signals upon detection of a fault in a memory cell; logic means coupled to the memory cells and to the sensing means for selecting the first or second word string in response to a fault signal; wherein upon detection of a fault in a first word string, the data word is written into the second word string; and a central shifting unit coupled to the memory array for reading a data word stored in a word string into the shifting unit, incrementing the data word, and writing the incremented data word into its respective word string.

Abstract: A memory cell comprising a bistable latch having first and second nodes, at least two non-volatile transistors (NV1, NV2) each having a source, a drain and a control gate, the control gates being connected to the first node (NODE 1) and one of the source and drain of each transistor being connected to the second node (NODE 2), each non-volatile transistor (NV1, NV2) further having a substrate and a floating gate between the control and the substrate, and switching means (N1, N2, TG1) for enabling the transistors to be checked in circuit.

Abstract: A memory cell is provided comprising a bistable latch (I1, I2) having first and second nodes (NODE 1, NODE 2) and a nonvolatile transistor (NV1). The control gate of the nonvolatile transistor is connected to the first node and either the source or drain is connected to the second node. A switching transistor is provided for maintaining the control gate and the substrate of the nonvolatile transistor at substantially the same potential during volatile operation of the latch, thereby reducing voltage stress which would lead to charge tunnelling to or from the floating gate. In this way, disturbance of the floating gate charge is avoided during volatile operation. The cell is particularly suited to silicon gate fabrication technology.

Abstract: A sense amplifier for determining the logic state of a memory cell consists of a switch transistor (N2) for receiving current during sensing from the memory cell (NV1), a nonvolatile transistor (NV2) providing a reference current which is compared to a representation of the sensed current through the switch transistor (itself dependent on the state of NV1), a bistable latch (N4P4, N5P5) which is switched into one or other of its states depending on the result of the comparison, and a feedback from the output of the latch (NODE 3) to the gate of the switch transistor (N2) to isolate the amplifier from the memory cell after sensing.

Abstract: An electronic counter such as for use in the odometer of a motor vehicle is provided comprising an array (10) of m rows and n columns of single flip-flop data latches and a central shifting unit (14). The central shifting unit (14) comprises a row of n data latches arranged to read data from and write data to each of the m rows of data latches of the array (10). In operation, the central shifting unit (14) reads data from a row of data latches of the array, performs a shift operation on the data and an invert operation on one of n data latches of the central shifting unit (14) and returns the data so operated on to the row of data latches in the array (10). By these steps, a counting operation in Johnson code is performed on the data. This invention uses less chip area than known counters.

Abstract: Insulating layers responsible for the trapping of electric charge in non-volatile semiconductor memories, such as FAMOS or MNOS, are fabricated as thicker layers when doped with metals having partially filled d or f electron shells. Typically the insulating layer is silicon oxide doped with up to 10 atomic % of a first transition series metal.

Abstract: Memory circuits having a floating gate transistor as a non-volatile storage element are constructed with a shunt transistor across the floating-gate transistor which in the event of a short circuit between the floating gate and the transistor substrate causes the memory to go into a predetermined fail-safe condition. The circuits are cross-coupled flip-flops with a driver and a complementary driver or load connected in series in each of the circuits, one driver or complementary driver or load being a floating gate transistor such as a FATMOS. Short circuiting of the floating gate to the control gate of the floating-gate transistor gives the same fail-safe condition.

Abstract: An NMOS non-volatile latch having N-channel drivers Q.sub.1 and Q.sub.2 and variable threshold N-channel FATMOS transistors Q.sub.3 and Q.sub.4 as depletion loads. The control gate of each FATMOS transistor is coupled to its own node (X.sub.1 or X.sub.2) so as to operate in depletion, whereas to obtain the correct voltage stresses the tunnels of the FATMOS floating gates are cross-coupled to the opposite latch nodes.

Abstract: One disclosed embodiment of the improved digital to analog converters in accordance with the invention comprises means for producing a first series of pulses whose average value is representative of a first group of the bits of an applied digital signal; means for producing a second series of pulses whose average value exceeds that of the first series of pulses by a preselected fixed amount; means for filtering the first and second series of pulses; and means for alternately applying the filtered first or second series of pulses to a smoothing circuit such that the percentage of the time respective ones of said filtered series of pulses are applied to the smoothing circuit is proportional to the value of the remaining bits of the applied digital signal. The output from the smoothing circuit is a direct voltage signal which is representative of the applied digital signal.

Abstract: A device for providing a selectively variable proportion of an electrical signal, which can be used instead of a conventional resistive track potentiometer, is disclosed. The device comprises two switching devices, typically CMOS transmission gates, connected in series between two inputs for receiving the electrical signal, an output at the series connection of the switching devices, and a control circuit for cyclically switching the switching devices between high and low conductivity states. The control circuit is so arranged that when one of the switching devices is in its high conductivity state, the other is in its low state and vice versa, and the control circuit is arranged to control selectively the relative durations that the devices remain in their different conductivity states.

Abstract: The invention concerns an internal combustion engine provided with a vacuum sensor for monitoring the level of partial vacuum in the engine's inlet manifold, in order to provide an indication of engine load. during changes in engine load, the level of partial vacuum presented to the vacuum transducer is modified from that obtaining in the inlet manifold in order to improve the accuracy of the output of the transducer during changes of engine load.

Abstract: A transducer responsive to a plurality of different parameters includes a plurality of sensing devices responsive to the parameters and arranged to combine two signals in relative proportions dependent upon the value of the parameter concerned. The two signals have the same frequency characteristic and are switched cyclically between different relative phases; typically the signals are switched between an in phase condition and a quadra-phase condition. A processing circuit is provided which compares the output of the different parameter sensing devices when the signals are in phase and in phase quadrature so as to derive output signals indicative of the values of the different parameters which are free of phase errors that would otherwise impair the output signals.

Abstract: An ignition system for an internal combustion engine which includes circuitry for generating a pulse of a duration which is substantially independent of engine speed within at least a predetermined speed range. Means are provided for varying the timing of said pulse at least in response to engine speed (and, in the preferred embodiment described, to load as measured by manifold vacuum) so that the end of the pulse occurs at the required angle in the engine cycle, in accordance with engine speed and possibly other inputs.In the preferred embodiment described, a read only memory stores engine angle signals which are converted into an appropriate delay by means of a programmed delay line.Means are also provided in the pulse generation circuit for protecting the components thereof from high overswing voltages.

Abstract: A signal combining circuit includes means for receiving a pair of digital waveforms of similar frequency and for producing a further waveform which is indicative by its phase of the relative amplitudes of the waveforms. A circuit arrangement is provided for reducing undesirable distortions of the shape of the further waveform, however this arrangement introduces undesirable phase modifications and means are provided for reducing the effect of these modifications. The relative phases of the two digital waveforms are, at a predetermined frequency, switched to one or other of two predetermined relationships and the phase of the further waveform obtained when one of the relationships occurs is compared with that obtained when the other relationship occurs in order to compensate for said modifications.