Abstract: A memory address controller addresses two memories and selectively modifies an address before it is applied to the addressing input of one of the two memories. A bit of the address is used to indicate to the controller if the address is to be modified. The same address is applied unchanged to the addressing input of the other of the two memories by the memory address controller. In this manner the addressing range is expanded.

Abstract: A multifunction arithmetic indicator that is associated with and controlled by an arithmetic logic unit (ALU) to store standard arithmetic indicator information such as overflow, carry, arithmetic sign and all bits equal zero that are generated by the ALU when processing binary information. A control unit sends control signals to multiplexers in the multifunction arithmetic indicator that cause the selection of appropriate arithmetic indicator information from the ALU, no matter what the bit length of binary words being processed by the ALU. The selected indicator information is stored in a register for later use.

Abstract: Memory failure detection apparatus is disclosed which is used with a large capacity memory that is organized in banks of memory, and with which error correction circuitry is used to correct correctable errors and provide an indication of same. The detection apparatus is responsive to the error indications and to a bank select addressing signal to provide and store error counts for a bank or banks of memory located on each memory board. A system processor periodically reads the error counts and responds to same to provide a maintenance message indicating that a specific memory board is to be replaced.