Abstract: A semiconductor device is formed having a trench adjacent to a current carrying region of the device. The trench is formed having a depth greater than the depth of a tub region of the device. Increasing the trench depth moves a region of higher field strength from the tub region to a region along the trench. The region along the trench does not have a junction and may withstand the higher field strength.

Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes removing a portion of a semiconductor material using an orientation-dependent etch to form a first cavity, a second cavity, wherein the first cavity is isolated from the second cavity, a first protrusion is between the first cavity and the second cavity, and the semiconductor material comprises silicon. The method further includes performing a thermal oxidation to convert a portion of the silicon of the semiconductor material to silicon dioxide and forming a first dielectric material over the first cavity, over the second cavity, over at least a portion of the semiconductor material, and over at least a portion of the first protrusion. Other embodiments are described and claimed.

Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes forming a portion of the unidirectional transistor and a portion of a bidirectional transistor in or over a semiconductor material simultaneously. Other embodiments are described and claimed.

Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes forming a portion of the unidirectional transistor and a portion of a bidirectional transistor in or over a semiconductor material simultaneously. Other embodiments are described and claimed.

Abstract: A semiconductor device is formed having lower gate-to-drain capacitance. The semiconductor device having an active region (1300) and a dielectric platform region (1310). A trench (80) is formed adjacent to a drain (20) of the semiconductor device to a first depth. The etch process for forming trench (80) etches the dielectric platform region (1310) to a first depth. A second trench (210) is etched in trench (80) to further isolate areas in the active region (1300). The etch process for forming the second trench (210) etches the dielectric platform region (1310) to form a support structure for the dielectric platform in the substrate. The dielectric platform, the trench (80), and the second trench (210) is capped and sealed. The dielectric platform is made approximately planar to the major surface of the substrate by forming the support structure from the first depth to the second depth.

Abstract: In various embodiments, semiconductor components and methods to manufacture these components are disclosed. In one embodiment, a method to manufacture a semiconductor component is disclosed. The semiconductor includes a heat sink and a semiconductor die that has a first terminal on a top surface of the semiconductor die, a second terminal on the top surface of the die, and a third terminal on the bottom surface of the die. The method includes attaching a first portion of a leadframe structure to the first terminal of the semiconductor die. The method further includes attaching the second terminal of the semiconductor die to the heat sink after the attaching of the first portion of the leadframe structure to the first terminal of the semiconductor die, wherein the leadframe structure is spaced apart from the heat sink and is electrically isolated from the heat sink. Other embodiments are described and claimed.

Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes removing a portion of a semiconductor material to form a first protrusion and a cavity having a boundary that is below a surface of the semiconductor material, wherein the first protrusion extends from the boundary of the cavity. The method further includes forming a non-conformal material over a first portion of the first protrusion using an angled deposition of the non-conformal material, wherein the angle of deposition of the non-conformal material is non-perpendicular to the surface of the semiconductor material. Other embodiments are described and claimed.

Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a capacitor embedded in a dielectric material below the surface of a semiconductor substrate is disclosed. Other embodiments are described and claimed.

Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a structure includes a dielectric material and a void below a surface of a substrate. The structure further includes a doped dielectric material over the dielectric material, over the first void, wherein at least a portion of the dielectric material is between at least a portion of the substrate and at least a portion of the doped dielectric material. Other embodiments are described and claimed.

Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes removing a portion of a semiconductor material to form a cavity that extends at least about one micron or greater below the surface of the semiconductor material, filling the cavity with a sacrificial material, forming a dielectric material over the sacrificial material and over at least a portion of the surface of the semiconductor material, and removing a portion of the dielectric material to form an opening to expose a portion of the sacrificial material, wherein the opening has a width that is substantially less than a width of the cavity and the dielectric material is rigid or substantially rigid. The method further includes removing the sacrificial material. Other embodiments are described and claimed.

Abstract: A semiconductor device having reduced input capacitance is disclosed. The semiconductor device includes a pedestal region having a gate overlying a sidewall of the pedestal region and gate interconnect overlying a major surface of the pedestal region. The pedestal region includes a conductive shield layer (260). The conductive shield layer (260) is isolated from the gate of the transistor by more than one dielectric layer (330, 340, and 350) to reduce input capacitance. The pedestal region includes an air gap region (1525) to further lower the dielectric constant of the pedestal region between the gate/gate interconnect and the conductive shield layer (260).

Abstract: A semiconductor device is formed having lower gate to drain capacitance. A trench (80) is formed adjacent to a drain (20) of the semiconductor device. Trench (80) has a sidewall surface (100) and a surface (90). A doped region (110) is implanted through the sidewall surface (100) of trench (80). A dielectric layer (150) overlies the sidewall surface (100) of trench (80). A shield layer (170) overlies the dielectric layer (150). The shield layer (170) is between a portion of drain (20) and a portion of the gate and gate interconnect of the semiconductor device thereby reducing gate to drain capacitance. The shield layer (170) overlies a minority portion of the surface (90) of trench (80). A second shield layer (270) further reduces gate to drain capacitance.

Abstract: A semiconductor device is formed having a pedestal. The pedestal includes at least two dielectric layers. The pedestal has a sidewall and a major surface. A conductive layer is formed overlying the pedestal. A vertical portion of the conductive layer adjacent to the sidewall of the pedestal is a gate of the transistor. The portion of the conductive layer overlying the major surface can be used as interconnect. The gate and gate interconnect are contiguous and formed in a single process. A conductive shield layer may be integrated into the pedestal. The conductive shield layer functions as a faraday shield that reduces gate to drain capacitance of the device.

Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes removing a portion of a semiconductor material using an electrochemical etch to form a first cavity, a second cavity, wherein the first cavity is isolated from the second cavity, a first protrusion is between the first cavity and the second cavity, and the semiconductor material comprises silicon. The method further includes performing a thermal oxidation to convert a portion of the silicon of the semiconductor material to silicon dioxide and forming a first dielectric material over the first cavity, over the second cavity, over at least a portion of the semiconductor material, and over at least a portion of the first protrusion. Other embodiments are described and claimed.

Abstract: In accordance with one or more embodiments, a semiconductor structure includes a semiconductor substrate, a first semiconductor material over the semiconductor substrate, and a second semiconductor material over a portion the first semiconductor material, wherein the second semiconductor material comprises silicon-germanium-carbon (SiGeC) and wherein the first semiconductor material is a silicon epitaxial layer. The semiconductor structure further includes an active device, wherein a portion of the active device is formed in the second semiconductor material and a dielectric structure extending from the first surface of the first semiconductor material into the semiconductor substrate through the first semiconductor material.

Abstract: Briefly, in accordance with one or more embodiments, a dielectric platform is at least partially formed in a semiconductor substrate and extending at least partially below a surface of a semiconductor substrate. The dielectric platform may include structural pillars formed by backfilling a first plurality of cavities etched in the substrate, and a second plurality of cavities formed by etching away sacrificial pillars disposed between the structural pillars. The second plurality of cavities may be capped to hermetically seal the second plurality of cavities to impart the dielectric constant of the material contained therein, for example air, to the characteristic dielectric constant of the dielectric platform. Alternatively, the second plurality of cavities may be backfilled with a material having a lower dielectric constant than the substrate, for example silicon dioxide where the substrate comprises silicon.

Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes forming a portion of the unidirectional transistor and a portion of a bidirectional transistor in or over a semiconductor material simultaneously. Other embodiments are described and claimed.

Abstract: A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a second electrode interconnection region overlying a second major surface. Each transistor cell has an approximately constant doping concentration in the channel region. A dielectric platform is used as an edge termination of an epitaxial layer to maintain substantially planar equipotential lines therein. The power transistor finds particular utility in radio frequency applications operating at a frequency greater than 500 megahertz and dissipating more than 5 watts of power. The semiconductor die and package are designed so that the power transistor can efficiently operate under such severe conditions.

Abstract: A semiconductor device is formed having a trench adjacent to a current carrying region of the device. The trench is formed having a depth greater than the depth of a tub region of the device. Increasing the trench depth moves a region of higher field strength from the tub region to a region along the trench. The region along the trench does not have a junction and may withstand the higher field strength.

Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a semiconductor structure having a silicon-on-insulator (SOI) substrate and a dielectric region is disclosed. The dielectric region is adjacent to the active layer of the SOI substrate and the dielectric region includes a portion of a buried oxide (BOX) layer of the SOI substrate. At least a portion of the dielectric region extends from a surface of the active layer of the SOI substrate to a depth of at least about three microns or greater below the surface of the active layer. Other embodiments are described and claimed.