Abstract: A successive approximation analog-to-digital converter utilizes an improved high-gain current comparator having a zero input impedance characteristic in combination with an equal current digital-to-analog converter. The zero input impedance comparator permits the use of low power C-MOS switching circuitry by leading the output of the digital-to-analog converter to the zero impedance input of the comparator, thereby overcoming the problem of decreased switching speed associated with high capacitance C-MOS outputs. The zero impedance current comparator includes an improved current-to-voltage converter having an overdrive shunt circuit to reduce quiescent current and to permit higher value load resistors for better gain; and cascaded current cells to provide increased gain.

Abstract: A transient-free, high accuracy digital-to-analog converter is disclosed having a resistor network which generates a plurality of equally weighted currents selectively switched to an output bus to provide an output corresponding to the input code, in which a binary input code is decoded into a specialized code such that an incremental increase in the input code causes an additional one of the equally weighted currents to be coupled to the output bus.

Abstract: A hybrid package which includes a plastic shell having an integral interior configuration for support of a ceramic substrate and terminal pins, and an encapsulate for rigid retention of the pins and for sealing of the package.

Abstract: A digital delay line for an analog signal having an improved efficiency in converting between the analog and digital signal formats. The delay line operates by converting an analog output into a representative series of binary ones and zeros which are applied through a shift register at a set clock rate. The shift register output, at a selected delay interval, is reconverted to the original analog levels. The conversions are governed by a logic network which increases the conversion efficiency to permit a lower clock rate and shorter shift register without a corresponding loss in frequency response.

Abstract: An audio system which achieves a concert hall reverberation effect from a stereo input signal. From two stereo input signals the audio system produces quadraphonic signals suitable for application to four speakers in the pattern of a quadraphonic sound reproduction system. The system applies the stereo input signals to a front pair of speakers substantially without alteration while reverberation is added to the stereo input signals for application to the rear speakers which realistically reproduces the impression of concert hall acoustics in the sound reaching the listener from all four speakers. The reverberation is provided by a channel signal delay scheme in combination with a channel interconnection network which achieves long reverberation times with a high echo density that eliminates objectionable, discrete echo effects.

Abstract: A delta-sigma converter and corresponding decoder employing predetermined characteristics of readily available logic elements. The converter is realized through the use of an integrator responding to an analog input signal and a dual D flip-flop package having a high impedance, comparator functioning input and low impedance output to act as a switch to control the integrator. Switching of the flip-flop acts to provide pulses at a rate corresponding to the analog input signal level.