Abstract: 4800 B/S full duplex operation of a frequency-multiplexing modem over the switched telephone network without cancellation is made possible by combining 900-baud, 32-state operation with a combination of analog filtering and raised cosine digital filtering and stop bit robbing.

Abstract: Filter quality is substantially improved (or complexity substantially reduced) in a digital PSK modem requiring an overall filter characteristic of the percent raised cosine type by using, in both the transmitter and the receiver, a filter having the same percent raised cosine response but at a higher cutoff frequency which satisfies the formula ##EQU1## where f.sub.f is the cutoff frequency (6 db) of the new filter, f.sub.o is one-half the baud rate of the modem, and .alpha. is the percent raised cosine expressed in decimal form.

Abstract: Error multiplication in the differential decoder and descrambler of V.22 bis modems is avoided by replacing the differential coding with forward error correction and single symbol coding. The error syndrome bit of the error corrector is used in establishing phase and timing synchronization by causing the receiver to try all possible combinations of phase and timing, and to lock onto the combination which produces a minimum of error syndrome bits. The descrambler receives the error-free corrected bit stream, whereby the descrambler's inherent error multiplication becomes moot.

Abstract: A fast learn modem comprising a transmitter for generating a fast learn preamble and applying the preamble to a communication channel and a receiver for receiving the fast learn preamble from the communication channel. The fast learn preamble includes a single impulse and the timing, phase and equalization characteristics of the receiver are adjusted in response to the single impulse so that the receiver can receive and process data.

Abstract: An apparatus for processing an information signal representative of information and containing phase error. The apparatus includes a detector for detecting the information in the signal and an error signal generator for generating an error signal representative of the error. A phase lock loop makes corrections which tend to reduce the phase error. The gain of the phase lock loop is adjusted in accordance with the error signal to optimize system performance.

Abstract: A touch sensitive switch arrangement with an I.sup.2 L (Integrated Injection Logic) structure includes a battery power source, a current limiter, an injector, a first-stage and second-stage switching transistors being both supplied with current from the injector, a first touch electrode connected to the positive polarity of the battery power source and a second touch electrode connected to the base of the first-stage switching transistor with electrical isolation from the first touch electrode.

Abstract: A phase tracking network comprising a phase correction network for correcting at least some of the phase error of an input signal to provide a phase corrected signal having components in first and second channels and a detector responsive to the phase corrected signal for providing a detected signal having first and second components in the first and second channels. An error calculator provides a phase correction signal back to the phase correction apparatus which responds to the phase correction signal to correct the phase error of the input signal. The phase error signal contains substantially no noise from the first channel at least when the first component of the detected signal is zero and contains substantially no noise from the second channel at least when the second component of the detected signal is zero.

Abstract: In a receiver, an analog-to-digital converter is adapted to sample a distorted analog signal to provide a plurality of distorted digital symbols separated in time by a particular interval. In an equalizer, taps are provided with variable multiplying coefficients which sequentially multiply the distorted digital symbols to provide undistorted digital symbols. A timing control network is responsive to variation in one of the multiplying coefficients to control the timing of the converter and hence the duration of the particular interval.

Abstract: A control system comprising a gain control circuit for adjusting the gain of an input signal to provide a gain controlled signal and an integrator for integrating the gain controlled signal to provide an output signal. A first circuit responds to a particular condition for changing the gain of the gain control circuit and a second circuit responds to that same condition for changing the output signal independently of the gain control signal to bring about a more rapid change in the output signal than could be brought about solely by changing the gain controlled signal.

Abstract: A data transmission system is provided with a double sideband suppressed carrier transmitter and receiver for transferring data between data processing apparatuses. The transmitter and receiver communicate over a telephone line which has physical characteristics which produce delay and attenuation distortion and phase jitter in the transmitted signal. The receiver includes a sampler for converting the transmitted signal into a digital signal, an automatic equalization network for correcting the delay and attenuation distortion, and a phase correction network compensating for frequency offset, phase offset, and phase jitter. The phase corrected and equalized signal is then detected and introduced to the data processing apparatus.An error signal calculator is responsive to the phase corrected signal and the detected signal to provide a system error signal for automatically updating the functions of the equalization and phase correction networks in accordance with the characteristics of the incoming signal.

Abstract: In a system for transmitting information between first and second data processing apparatuses, a signaling scheme provides a digital data signal with in-phase components and quadrature components which define a plurality of vectors. The vectors, when plotted on a graph having an abscissa and an ordinate, each have a minimum separation distance defined by the radius of a circle having its center at the tip of the associated vector. The circles of the vectors, which are aligned in rows substantially parallel to the abscissa or the ordinate of the graph, are tangential to the adjacent circles. Boundary areas associated with the respective vectors are defined by boundary lines extensions of which pass through points defined by the vector components. This signaling scheme minimizes vector magnitude, associated with minimum power, while maximizing vector separation distance, associated with reduced detection error.

Abstract: A demodulator for detecting first and second frequencies in an analog input signal includes a limiter providing first pulses having a short duration in response to the first frequency and having a long duration in response to the second frequency. A first counter provides a first reference signal including second pulses, and a second counter provides a second reference signal including third pulses. Logic means responsive to the second and third pulses provide a signal including fourth pulses during periods corresponding to the first frequency and a signal including fifth pulses during periods corresponding to the second frequency. An up-down counter is responsive to the fourth pulses to provide a first output signal and responsive to the fifth pulses to provide a second output signal. The fourth and fifth pulses have frequencies and durations providing the counter with substantially equal counting rates during the periods corresponding to the first and second frequencies of the analog signal.

Abstract: A printer comprising a supporting structure and a print disc having a curved peripheral surface with characters formed thereon. The print disc is mounted on the supporting structure for rotation about a rotational axis. Paper is moved over the peripheral surface in a direction generally parallel to the rotational axis, and one or more hammers cooperate with the paper and the characters for effecting printing on the paper. A guide generally conforms the paper to at least a portion of the curved peripheral surface as the paper is moved over the peripheral surface. This permits an entire line of characters to be printed and provides the paper with some rigidity against bending and an ability to extend generally vertically to permit the user to visually observe what has been printed. To eliminate noise during standby, the print disc is rotated through only one revolution in response to each print command.

Abstract: A phase tracking network for correcting an undesirable first phase angle of a first signal, includes an error calculating circuit responsive to partial response data signals to provide a phase error signal. Filter means adapted to be coupled to the error calculating circuit is responsive to the linear and nonlinear characteristics of the phase error signal to provide a second phase angle in a second signal. A phase correction network coupled between the filter means and the error calculating circuit is responsive to the second phase angle in the second signal to correct the first phase angle in the first signal.

Abstract: A receiver includes means for sampling and noncoherently demodulating a received signal to provide digital symbols in each of a first and second channel. An equalization network equalizes the incoming signal and a phase correction network corrects the phase of the equalized signal. In response to the transmission of a preamble in the first channel, a fast learn network derives the phase error by determining the arc tangent of a quotient formed by dividing the signal in the first channel by the signal in the second channel. A course phase jump can be made to insure that the arc tangent is not greater than unity. The timing error of the sampling means can be derived by determining the arc tangent of a quotient formed by dividing the present digital symbol in the one channel by the preceding digital symbol in the one channel.

Abstract: An automatic digital modem receiving an input analog signal samples the input signal to provide a random multilevel data signal. This multilevel signal is equalized and phase corrected so that the characteristics of the modem are substantially synchronized with the characteristics of the input analog signal. A system error signal which is responsive to the random multilevel data signal is averaged to provide a synchronization quality signal. When the synchronization quality signal degrades to a predetermined magnitude, a restart signal adjusts the sampling, the equalization, and the phase correction of the modem to reduce the magnitude of the synchronization quality signal. The associated method includes the steps of adjusting only the phase correction of the modem for a particular interval of time and then jumping the sampling of the modem if the synchronization quality signal has not been reduced below the first predetermined magnitude.

Abstract: In a logic cell, a plurality of gates are serially connected and responsive to signals on a plurality of conductors to perform a particular logic function. The gates are responsive to subsystem clock signals which control the operation of the gates to delay the output of the logic cell. The cell includes at least one ratioless gate, and at least one ratioed gate. The ratioless gates provide high speed and reduced size, while the ratioed gates provide low noise characteristics. In combination, the ratioed gates, which provide strong output signals, make excellent drivers for the ratioless gates which are particularly adapted to accommodate complex logic networks.

Abstract: A transmitter transmits data through a communication channel to a receiver and the communication channel provides the data with delay and attenuation distortion. The receiver includes an equalization network having taps with multiplying coefficients for correcting the delay and attenuation distortion of the data. In response to a special sequence of the data, either specially generated by the transmitter or detected in random data, the receiver generates signals for updating the multiplying coefficients of the taps and these signals are introduced to the equalization network through a gate enabled by a special sequence detection network. This apparatus provides for the adjustment of the equalization taps in an extremely short period of time such as 5.83 milliseconds.

Abstract: An Automatic Gain Control responsive to an input analog signal having a significantly varying power level provides an output analog signal of substantially constant power level. An analog-to-digital converter samples the output analog signal and expresses the amplitude of the samples in digital words characterized by bits including a Most Significant Bit. The Automatic Gain Control is responsive to the digital characteristics of at least the Most Significant Bit of the digital words to amplify the output analog signal to the substantially constant power level. This permits amplification of the input signal to a level approaching the maximum level expressible by the digital words and significantly reduces the quantization noise of the converter by maximizing the number of digital words which are available to express the signal amplitude.