Abstract: A hierarchical word line driving structure is disclosed that uses a single global word line and low power sub-word line driver circuits that are relatively small in size. Higher density memory cell arrays are made possible by inverting the signal on a global word line inside each sub-word line driver circuit.
Type:
Grant
Filed:
February 6, 1997
Date of Patent:
February 23, 1999
Assignee:
Hyndai Electronics America
Inventors:
Jong-Hoon Oh, Joon-Ho Kim, Jinyong Chung