Abstract: A nonvolatile ferroelectric memory device includes a plurality of sense amplifiers, top and bottom cell array units disposed respectively at an upper and a lower sections, the top and bottom cell array units each including a plurality of unit cells, and being disposed symmetrically about the sense amplifiers. The nonvolatile ferroelectric memory device further includes at least one top reference array unit, at least one bottom reference array unit, a plurality of main bit lines connected to the unit cells of the top or bottom cell array unit, and a plurality of reference bit lines of the bottom or top cell array unit. Reference bit lines of the top or bottom cell array unit correspond to main bit lines of the bottom or top cell array unit disposed symmetrically about the sense amplifiers.