Abstract: A memory device includes a pre-charge transistor for connecting/disconnecting the input line of a global data line driver to a supply voltage line. To reduce the flow of current through the pre-charge transistor even in a stand-by state, the pre-charge transistor is turned on when, at a same time, an enabling signal of a page buffer is asserted, and a low voltage functioning mode is selected and the memory device is not in a stand-by state. Alternatively, the memory device may be in a stand-by state but the datum read from the memory is high. The pre-charge transistor is securely turned off in all other cases.

Abstract: A bit line of a semiconductor device includes a first interlayer dielectric film disposed on a semiconductor substrate, a plurality of bit line stacks disposed on the first interlayer dielectric film, a plurality of bit line spacers disposed on side walls of the bit line stacks, and a buffer film disposed on the bit line spacers, the first interlayer dielectric film and the bit line stacks; and a method for fabricating the same.

Abstract: The present invention provides a semiconductor memory device capable of being stably operated by reducing power noise generated while a sense amplifier performing for sensing and amplifying data supplied to a bit line. For this object, an inventive semiconductor memory device includes a cell array having a plurality of cells; a plurality of bit lines supplied with voltage stored in the plurality of the cells; a plurality of sense amplifier block for sensing and amplifying a voltage of the plurality of the bit lines, each bit line being connected to each cell; a plurality of switches for selectively connecting or disconnecting the plurality of the sense amplifier block to the plurality of the bit lines; and a sense amplifier control block for turning on the plurality of the switches by using at least two different timing sets.