Abstract: A method for fabricating a capacitor of a semiconductor device includes sequentially forming an etch-stop layer and a mold layer over a substrate, sequentially forming a support layer and a hard mask pattern over the mold layer, forming a storage node hole by etching the support layer and the mold layer using the hard mask pattern as an etch barrier, forming a barrier layer on the sidewall of the mold layer inside the storage node hole, etching the etch-stop layer under the storage node hole, forming a storage node inside the storage node hole, and removing the hard mask pattern, the mold layer, and the barrier layer.

Abstract: A data processing apparatus includes a pre-fetch unit configured to divide and store data, a validation setting unit configured to store information regarding whether or not the data stored in the pre-fetch unit are valid, an address generation unit configured to generate an address for reading/storing the data from/in the pre-fetch unit, and a pre-fetch control unit configured to control a storage position of the data in the pre-fetch unit by using the address and information of the address generation unit and the validation setting unit.

Abstract: A dual polysilicon gate of a semiconductor device includes a substrate having a first region, a second region, and a third region, a channel region with a recessed structure formed in the first region of the substrate, a gate insulating layer formed over the substrate, a first polysilicon layer filled into the channel region, and formed over the gate insulating layer of the first and second regions, a second polysilicon layer formed over the gate insulating layer of the third region, and an insulating layer doped with an impurity, and disposed inside the first polysilicon layer in the channel region.

Abstract: A voltage supply apparatus includes a power noise sensing unit, a voltage selecting unit, a first power voltage supply unit and a second power voltage supply unit. The power noise sensing unit senses noise from first and second powers and outputs a power noise sensing signal. The voltage selecting unit outputs first and second driving signals in response to a voltage-supply-enable-signal and the power noise sensing signal. The first power voltage supply unit applies a voltage of the first power in response to the first and second driving signals. The second power voltage supply unit applies a voltage of the second power in response to the first and second driving signals.

Abstract: An integrated circuit includes a CML swing reference voltage generating unit, a CML bias control voltage generating unit and a CML buffering unit. The CML swing reference voltage generating unit determines a level of a CML swing reference voltage in response to a frequency setting code and a CML bias control voltage. The CML bias control voltage generating unit compares the level of the CML swing reference voltage with a level of a CML target reference voltage and determines a level of the CML bias control voltage based on the comparison result. The CML buffering unit generates a CML output signal swinging in a CML region by buffering an input signal and determines a swing level of the CML output signal on the basis of the level of the CML swing reference voltage in response to the frequency setting code and the CML bias control voltage.

Abstract: A semiconductor device includes a clock input block to receive a system clock and a data clock, a clock frequency dividing block to generate a plurality of multi-phase data frequency division clocks each of which has the phase difference of a predetermined size by dividing a frequency of the data clock and to determine whether or not phases of the plurality of multi-phase data frequency division clocks are reversed in response to a frequency division control signal, and a first phase detecting block to detect a phase of the system clock based on a phase of a first selected clock that is predetermined among the plurality of multi-phase data frequency division clocks and to determine a logic level of the frequency division control signal in response to the detected result.

Abstract: A capacitor with zirconium oxide and a method for fabricating the same are provided. The method includes: forming a storage node; forming a multi-layered dielectric structure on the storage node, the multi-layered dielectric structure including a zirconium oxide (ZrO2) layer and an aluminum oxide (Al2O3) layer; and forming a plate electrode on the multi-layered dielectric structure.

Abstract: Disclosed is a method for fabricating a contact in a semiconductor device, including: obtaining a pattern layout including bit lines arranged across a cell matrix region of a semiconductor substrate, cell storage node contacts arranged to pass through a portion of a first interlayer insulation layer between the bit lines, and dummy storage node contacts additionally arranged in an end of the arrangement of the cell storage node contacts; and forming the cell storage node contacts and the dummy storage node contacts using the pattern layout.

Abstract: A nonvolatile memory device and its fabrication method of the present invention may ensure a margin of the threshold drive voltage during a design process of the device by forming a resistance layer determining phase of ReRAM along an upper edge of a lower electrode, and improve operating characteristics of the device

Abstract: A method of manufacturing a flash memory device includes providing a substrate having an insulating layer, a first mask layer over the insulating layer, a second mask layer over the first mask layer, a first photoresist pattern over the second mask layer, the first photoresist pattern having a first pitch. A material layer is provided over the first photoresist pattern. The material layer is etched to convert the material layer into a material layer pattern having a second pitch that is less than the first pitch. The second hard mask layer is etched using the material layer pattern to form a second hard mask layer pattern that extends along a first direction. A second photoresist pattern is etched, the second photoresist pattern defining a first region that is not exposed and a second region that is exposed, the second region extending along a second direction that is orthogonal to the first direction.

Abstract: A nonvolatile memory device and a fabrication method thereof are disclosed. The nonvolatile memory device comprises a tunnel insulating film formed on an active region of a semiconductor substrate, a first conductive layer for a floating gate formed on the tunnel insulating film, a dielectric layer formed on the first conductive layer, a second conductive layer for a control gate formed on the dielectric layer, an etch-stop layer formed on the second conductive layer, and a gate electrode layer formed on the etch-stop layer. Accordingly, there is no difference in the degree to which the conductive layer under the gate electrode layer is etched when etching the gate electrode layer of the memory cell region and the peri region.

Abstract: A method of forming a hardmask pattern over a semiconductor device semiconductor device includes forming a first hardmask layer over a semiconductor substrate. First and second structures are formed over the first hardmask layer, the first and second structures formed of the same material, the first and second structures defining a first pitch. First and second overcoats are formed over the first and second structures, respectively, the first and second overcoats being conformal to the first and second structures, respectively. The first and second overcoats define a space therebetween and are configured to expose an underlying layer. A filling layer is formed to fill the space defined between the first and second overcoats. The first and second overcoats are removed to provide the first structure, the second structure, and a third structure provided between the first and second structures, the first and third structures defining a second pitch, the second and third structures defining a third pitch.

Abstract: A method of forming a bit line of a semiconductor device wherein an etch-stop nitride film, a trench oxide film and a hard mask nitride film are formed on a semiconductor substrate. The hard mask nitride film and the trench oxide film are etched to a limited etch thickness of a photo mask. The remaining trench oxide film is etched using the hard mask nitride film as a mask, thus forming a trench. The etch-stop nitride film and the hard mask nitride film are etched on condition that an oxide film has a high selectivity with respect to a nitride film. Accordingly, the loss of a top surface of the trench oxide film can be minimized and a bit line can be formed to have a uniform height. In accordance with the invention, bit line resistance and capacitance variation can be reduced and the reliability of a device can be improved.

Abstract: A data output control apparatus and method of a semiconductor memory device exactly synchronize the first read data with a clock signal by solving a problem that the first read data is faster than the clock signal as much as a transit time from a voltage level Vddq/2 to a power voltage Vddq or a ground voltage Vssq.

Abstract: TIMD (tetraisopropyl methylene diphosphonate) as a light absorbance depressant to a light source of a wavelength of less than 200 nm, and a photoresist composition containing the same are disclosed. The disclosed chemically amplified photoresist composition containing TIMD is useful for a VUV (vacuum ultraviolet) photoresist composition due to its low light absorbance to a light source of a wavelength of 157 nm.

Abstract: Methods of manufacturing flash memory cells. During a cleaning process after an etching process for forming a control gate is performed, polymer remains at the sidewall of a tungsten silicide layer. Therefore, the sidewall of the tungsten silicide layer is protected from a subsequent a self-aligned etching process. In addition, upon a self-aligned etching process, the etch selective ratio of the tungsten silicide layer to a polysilicon layer is sufficiently obtained using a mixed gas of HBr/O2. Therefore, etching damage to the sidewall of the tungsten silicide layer can be prevented. As a result, reliability of the process and an electrical characteristic of the resulting device are improved.

Abstract: A method of manufacturing a flash memory cell. The method includes controlling a wall sacrificial oxidization process, a wall oxidization process and a cleaning process of a trench insulating film that are performed before/after a process of forming the trench insulating film for burying a trench to etch the trench insulating film to a desired space. Therefore, it is possible to secure the coupling ratio of a floating gate by maximum and implement a device of a smaller size.

Abstract: The present invention relates to a boosting circuit. A boosting voltage (VBOOT) is dropped to a given voltage level through a pre-select clamp circuit and the boosting voltage (VBOOT) is again dropped through a clamp circuit, depending on the power supply voltage, so that a final target word line voltage is generated. Accordingly, a read access time is rapid upon a read operation, the current consumption is minimized and a stabilized word line voltage can be generated.

Abstract: The present invention relates to a supply voltage level detector. The supply voltage level detector includes a reference voltage generator for generating the reference voltage of a constant level depending on a control signal, a compare voltage generator for generating a compare voltage the variation ratio of which is higher than the supply voltage supplied from the outside depending on the control signal, and a comparator for comparing the reference voltage and the compare voltage depending on the control signal to output a given signal. The present invention constructs the compare voltage generator in the supply voltage level detector so that the variation of the compare voltage depending on the variation of the supply voltage becomes great. Therefore, the present invention can improve the sensing margin of the comparator for sensing the difference between the reference voltage and the compare voltage. Also, the present invention can prevent erroneous operation by a noise to accomplish a stable operation.

Abstract: A semiconductor device and method for fabricating a semiconductor device yields improved doping efficiency and increased capacitance. The method includes forming a silicon film on a substrate. HSG having a spherical projection forms on a surface of the silicon film. The surface of the silicon film having the HSG is washed, and a lower electrode forms by a doping process. A dielectric film and an upper electrode are sequentially formed on the silicon film without washing.