Patents Assigned to Hynix Semiconductor Inc.
  • Programming method of non-volatile memory device
    Patent number: 8711630
    Abstract: A programming method of a non-volatile memory device that includes a string of memory cells with a plurality of floating gates and a plurality of control gates disposed alternately, wherein each of the memory cells includes one floating gate and two control gates disposed adjacent to the floating gate and two neighboring memory cells share one control gate. The programming method includes applying a first program voltage to a first control gate of a selected memory cell and a second program voltage that is higher than the first program voltage to a second control gate of the selected memory cell, and applying a first pass voltage to a third control gate disposed adjacent to the first control gate and a second pass voltage that is lower than the first pass voltage to a fourth control gate disposed adjacent to the second control gate.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: April 29, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Seiichi Aritome, Hyun-Seung Yoo, Sung-Jin Whang
  • Semiconductor memory device and method for driving the same
    Patent number: 8710886
    Abstract: A semiconductor memory device has a duty cycle correction circuit capable of outputting a duty cycle corrected clock and its inverted clock having substantially exactly 180° phase difference therebetween. The semiconductor memory device includes a duty cycle corrector configured to receive a first clock and a second clock to generate a first output clock and a second output clock whose duty cycle ratios are corrected in response to correction signals, and a clock edge detector configured to generate the correction signals corresponding to an interval between a reference transition timing of the first output clock and a reference transition timing of the second output clock.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: April 29, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kyung-Hoon Kim, Jun-Woo Lee, Taek-Sang Song
  • Semiconductor memory device, test circuit, and test operation method thereof
    Patent number: 8713383
    Abstract: A semiconductor memory device includes a plurality of banks, each including a plurality of first memory cells and a plurality of second memory cells; a first input/output unit configured to transfer first data between the first memory cells and a plurality of first data pads; a second input/output unit configured to transfer second data between the second memory cells and a plurality of second data pads; a path selection unit configured to transfer the first data, which are input through the first data pads, to both the first and second memory cells during a test mode; and a test mode control unit configured to compare the first data of the first and second memory cells, and to control at least one of the first data pads to denote a fail status based on a comparison result, during the test mode.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: April 29, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Chang-Ho Do, Yeon-Woo Kim
  • Semiconductor memory system having ECC circuit and controlling method thereof
    Patent number: 8713407
    Abstract: A semiconductor memory system includes a memory area and an error-correcting (ECC) circuit. The memory area includes a plurality of cells, and the ECC circuit is configured to determine whether uncorrectable error data exists or not by using a parity according to cell data of the memory area in a read mode and a parity according to an encoding result of corrected data of the cell data.
    Type: Grant
    Filed: December 24, 2009
    Date of Patent: April 29, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jun Rye Rho
  • Delay locked loop
    Patent number: 8704561
    Abstract: A delay locked loop includes a delay adjusting unit configured to delay a first clock signal in outputting a second clock signal phase-locked with the first clock signal and generate a delay control signal in response to the first clock signal and the second clock signal and a variable delay line configured to output a third clock signal by delaying the first clock signal in response to the delay control signal.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: April 22, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hye-Young Lee, Yong-Mi Kim
  • Semiconductor memory system and method for driving the same
    Patent number: 8705295
    Abstract: A method for driving a semiconductor memory device includes controlling a plurality of erase voltages for a plurality of memory blocks, respectively, comparing the plurality of controlled erase voltages, and determining whether or not to enable the plurality of memory blocks for a subsequent write operation in response to a result of the comparison.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: April 22, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Min Min
  • Semiconductor memory device and driving method thereof
    Patent number: 8699295
    Abstract: A semiconductor memory device includes a plurality of wordlines and a driver configured to, when an wordline of the plurality of wordlines is activated by an active command, drive at least one non-activated wordline neighboring the activated wordline and remaining non-activated wordlines with different wordline driving voltage levels during a period of time that the activated wordline is driven to a high voltage level.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: April 15, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Myoung-Jin Lee, Jin-Hong An
  • Semiconductor device having a plurality of repair fuse units
    Patent number: 8698276
    Abstract: A semiconductor system includes a controller; a semiconductor device comprising a plurality of stacked semiconductor chips stacked over the controller, and a plurality of through-silicon vias (TSVs) configured to commonly transfer a signal to the plurality of stacked semiconductor chips; and a defect information transfer TSV configured to transfer TSV defect information sequentially outputted from at least one of the semiconductor chips to the controller, wherein the controller comprises: a plurality of first repair fuse units configured to set first fuse information based on the TSV defect information; and a plurality of first TSV selection units configured to selectively drive the TSVs in response to the first fuse information.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: April 15, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jeong-Woo Lee, Hyung-Dong Lee, Sang-Hoon Shin, Hyang-Hwa Choi
  • Semiconductor device and method for forming the same
    Patent number: 8699290
    Abstract: A method for forming a semiconductor device is disclosed. An anti-fuse is formed at a buried bit line such that the area occupied by the anti-fuse is smaller than that of a conventional planar-gate-type anti-fuse, and a breakdown efficiency of an insulation film is increased. This results in an increase in reliability and stability of the semiconductor device. A semiconductor device includes a line pattern formed over a semiconductor substrate, a device isolation film formed at a center part of the line pattern, a contact part formed at both sides of the line pattern, configured to include an oxide film formed over the line pattern, and a bit line formed at a bottom part between the line patterns, and connected to the contact part.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: April 15, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jung Sam Kim
  • Semiconductor device and method of manufacturing the same
    Patent number: 8692376
    Abstract: A method of manufacturing a semiconductor device includes forming an interlayer dielectric layer, forming trenches by etching the interlayer dielectric layer, forming a copper (Cu) layer to fill the trenches, and implanting at least one of an inert element, a nonmetallic element, and a metallic element onto a surface of the Cu layer.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: April 8, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jung Geun Kim, Whee Won Cho, Eun Soo Kim
  • Control circuit and operating method thereof
    Patent number: 8694818
    Abstract: A control circuit includes a plurality of clock synchronization units configured to shift an input signal in response to clock signals which are inputted thereto, a selection output block configured to select an output signal from output signals of the plurality of clock synchronization units, and output the selected output signal, and a clock supply block configured to sequentially supply the clock signals to the plurality of clock synchronization units.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: April 8, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Choung-Ki Song
  • Method for manufacturing a semiconductor device
    Patent number: 8685627
    Abstract: A method for manufacturing a semiconductor device includes forming an etch-target layer over a semiconductor substrate having a lower structure, forming a first mask pattern over the etch-target layer, forming a spacer material layer with a uniform thickness over the etch-target layer including the first mask pattern, forming a second mask pattern on an indented region of the space material layer, and etching the etch-target layer with the first mask pattern and the second mask pattern as an etch mask to form a fine pattern.
    Type: Grant
    Filed: November 6, 2008
    Date of Patent: April 1, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ki Lyoung Lee, Cheol Kyu Bok, Keum Do Ban, Jung Gun Heo
  • Semiconductor device including capacitor and contact plug
    Patent number: 8686541
    Abstract: The present invention provides technology directed to a semiconductor device and a method of manufacturing the same. According to the present invention, metal contact plugs are formed to come into contact with both sidewalls of a capacitor, including lower electrodes, dielectric layers, and an upper electrode. Accordingly, contact resistance can be reduced because the contact area of the upper electrode and the metal contact plugs forming the capacitor, can be increased. Furthermore, the number of chips per wafer can be increased because the area in which the metal contact plugs and the capacitor are formed can be reduced. In addition, the generation of noise can be reduced because the contact area of the capacitor and the metal contact plugs is increased and thus voltage at the upper electrode is stabilized.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: April 1, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jai Yong Woo
  • Method of forming metal line of semiconductor device
    Patent number: 8685852
    Abstract: A semiconductor device and a method of forming a metal line of a semiconductor device includes a first insulating layer formed over a semiconductor substrate an etch-stop layer formed over the first insulating layer, contact holes formed by etching the etch-stop layer and the first insulating layer, Contact plugs formed within the contact holes and a second insulating layer formed over the contact plugs and the etch-stop layer. The second insulating layer is etched in order to form trenches through which the contact plugs are exposed. Metal lines are formed within the trenches. Accordingly, since a hard mask with a high dielectric constant does not remain between the metal lines, the capacitance of the metal lines can be reduced.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: April 1, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jin Gu Kim
  • Phase-change random access memory device and method of manufacturing the same
    Patent number: 8686385
    Abstract: The PCRAM device includes a semiconductor substrate including a switching device; an interlayer insulating layer having a heating electrode contact hole exposing the switching device, a heating electrode formed to be extended along a side of the interlayer insulating layer in the heating electrode contact hole, wherein the heating electrode has a width gradually increased toward a bottom of the heating electrode and is in contact with the switching device, first and second phase-change layers formed within the heating electrode contact hole that includes the heating electrode, and a phase-change separation layer formed in the heating electrode contact hole between the first and second phase-change layers.
    Type: Grant
    Filed: December 27, 2011
    Date of Patent: April 1, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jin Seok Yang, Ha Chang Jung
  • Semiconductor cell and method for forming the same
    Patent number: 8674473
    Abstract: A semiconductor cell includes storage node contact plugs disposed on a semiconductor substrate, a bit line formation area which is disposed between the storage node contact plugs and exposes the semiconductor substrate, and an air gap which is in contact with a lower portion of a sidewall of the bit line formation area and extends in a direction perpendicular to a direction in which the bit line formation area extends. Therefore, the coupling effect between adjacent bit lines as well as the coupling effect caused between adjacent storage node contact plugs and the coupling effect caused between the storage node contact plug and the bit line are controlled to improve characteristics of semiconductor devices.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: March 18, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Song Hyeuk Im
  • Semiconductor memory device
    Patent number: 8675421
    Abstract: A semiconductor memory device includes a first page buffer group including a plurality of page buffers coupled to memory cells of a first memory array through bit lines, a second page buffer group, a coupling circuit configured to couple an output terminal and an inverse output terminal of a selected page buffer of the first page buffer group to a first local I/O line and a first inverse local I/O line, respectively, or an output terminal and an inverse output terminal of a selected page buffer of the second page buffer group to a second local I/O line and a second inverse local I/O line, respectively, in response to a column select signal, and a sense amplifier configured to detect a voltage difference between the first local I/O line and the first inverse local I/O line or between the second local I/O line and the second inverse local I/O line.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: March 18, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Yong Deok Cho
  • Nonvolatile memory cell, nonvolatile memory device and method for driving the same
    Patent number: 8675402
    Abstract: A nonvolatile memory cell is able to reduce the size per the unit area by employing a dual gate structure where the chalcogenide compound is used for a channel. The nonvolatile memory cell includes a phase-change layer, a first and a second gate that are in contact with sides of the phase-change layer to face each other across the phase-in change layer and control a current flowing through the phase-change layer by each gate being arranged to induce the phase transition of the phase-change layer independently of the other.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 18, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hae-Chan Park, Gap-Sok Do, Jang-Uk Lee
  • Memory device having resistance unit
    Patent number: 8675386
    Abstract: A memory device includes a memory unit including a plurality of first conductive lines and a plurality of second conductive lines that cross the first conductive lines, and a driving unit module coupled with the plurality of the first conductive lines through respective ones of a plurality of contacts and coupled with and the plurality of the second conductive lines through respective ones of the plurality of contacts, wherein as the first conductive lines become farther from the driving unit module along a direction that the second conductive lines extend, the respective contacts of the first conductive lines have lower resistance values.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: March 18, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seok-Pyo Song
  • Nonvolatile memory device and method for operating the same
    Patent number: 8677053
    Abstract: A nonvolatile memory device includes a selecting unit configured to select one of a read data or a program signal indicating a program period, an output unit configured to output an output signal of the selecting unit to the outside of a chip, and an output pin connected to the output unit.
    Type: Grant
    Filed: June 22, 2009
    Date of Patent: March 18, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ji-Hyae Bae, Kyoung-Wook Park