Abstract: A method for manufacturing a semiconductor device is disclosed. A method for manufacturing a semiconductor device includes forming a device isolation structure for defining an active region, forming a buried word line traversing the active region, forming one or more insulation film patterns over the buried word line, forming a line pattern including a first conductive material at a position between the insulation film patterns, and forming a plurality of storage node contacts (SNCs) by isolating the line pattern. As a result, when forming a bit line contact and a storage node contact, a fabrication margin is increased.

Abstract: A semiconductor device comprises a fuse having a blowing region at a center part for selectively connecting different two terminals; and a dummy contact positioned under the blowing region for forming empty space by being removed together with the blowing region in a blowing process.

Abstract: A voltage adjustment circuit of a semiconductor memory apparatus includes a control voltage generating unit configured to distribute an external voltage for selectively outputting a plurality of distribution voltages as a control voltage in response to a control signal, the plurality of the distribution voltages each have different voltage levels, a comparing unit configured to include a voltage supply unit configured to control an external voltage supplied to a first node and a second node if a level of an output voltage is higher than a level of a reference voltage in response to a level of the control voltage, and a detection signal generating unit configured to drop potential levels of the first and second nodes according to the levels of the output voltage and the reference voltage, and to output the potential level of the second node as a detection signal, and a voltage generating unit configured to drive the external voltage according to a potential level of the detection signal and to output the exter

Abstract: A high integration phase change memory device includes a semiconductor substrate including an access device, a heating electrode formed on the access device, a phase change nano band formed on the heating electrode, and an interlayer insulating layer for supporting the phase change nano band formed in both sides of the phase change nano band.

Abstract: A method of fabricating a semiconductor device includes forming a mask pattern over a semiconductor substrate to define a channel region. A portion of the semiconductor substrate is etched using the mask pattern as an etching mask to form a first pillar. A spacer is formed over a sidewall of the mask pattern and the first pillar. A portion of the semiconductor substrate exposed between the first pillars is etched using the spacer and the mask pattern as an etching mask to form a second pillar elongated from the first pillar. A portion of the second pillar is selectively etched to form a third pillar. The spacer and the mask pattern are removed. An impurity is implanted into an upper part of the first pillar and the semiconductor substrate between the third pillars to form a source/drain region. A surrounding gate is formed over an outside of the third pillar.

Abstract: A nonvolatile ferroelectric memory device has a single-ended sensing structure. The nonvolatile ferroelectric memory device comprises a plurality of cell array blocks, a plurality of sense amplifiers, a main amplifier unit and a data bus. The sense amplifier unit sets a voltage of a main bit line to a predetermined sensing level before cell data are transmitted to the main bit line, and then senses data by comparing the voltage of the main bit line with the sensing level when cell data are transmitted. Additionally, a data bus which is divided into a local data bus and a global data bus transmits the sensed data, thereby improving the sensing speed and the sensing margin.

Abstract: The present invention discloses a method and device for preserving a word line pass bias using a ROM block in a NAND-type flash memory. The method for preserving the word line pass bias includes a step for closing a precharge transistor of a precharge circuit before the operation of a pass transistor for precharging a selected word line, by separately outputting from the ROM block a program precharge control signal transmitted to a group access signal generation circuit for outputting a group access signal and a program precharge control signal transmitted to a block word line, and synchronizing the signals in a synchronization circuit. Accordingly, time mismatching in the program and read operations of the NAND-type flash memory is prevented, and a predetermined voltage precharged to the selected block word line is precisely inputted to a specific cell and preserved.

Abstract: The present invention discloses improved semiconductor device and method for manufacturing wherein one side of a source and drain region and a portion of a channel region are disposed on a buried oxide layer formed on a semiconductor substrate and the side of the source and drain region and another portion of the channel region are disposed on a Si epitaxial layer formed on a semiconductor substrate.

Abstract: In fabricating a capacitor of a semiconductor device, a first contact plug is formed in a plug contact hole formed by patterning a portion of a first interlayer insulating film formed on a substrate. A first barrier layer, a first polysilicon layer, and a second barrier layer are formed. A first contact hole is formed after sequentially patterning the second barrier layer, the first polysilicon layer, and the first barrier layer. A first dielectric layer is formed to have portions located at outside and bottom parts of the first contact hole. A second polysilicon layer is formed to have its portions located at portions except for the first contact hole. A second dielectric layer and a third polysilicon layer are formed. A second interlayer insulating film is formed after patterning the third polysilicon layer.

Abstract: The disclosed nonvolatile ferroelectric memory control device is configured to control an internal memory dump when a ferroelectric memory is used as an internal memory in a SOC (system on a chip) structure. In order to normally process internal memory data in normal and dump modes, dump mode control circuits comprise FRAM code cells, and external memory regions are allotted to internal memory regions so that all internal addresses may use ports normally. As a result, operation characteristics can be changed in the SOC structure by using a software way.