Abstract: In a method of operating a nonvolatile memory device, at least one among memory cell blocks of the nonvolatile memory device is designated as a content addressable memory (CAM) block which includes a plurality of CAM cells coupled to respective word lines of the nonvolatile memory device. Chip information for operations of the nonvolatile memory device is stored in the CAM cells which are coupled to a selected word line, whereas the remaining CAM cells of the CAM block are in an erased state.

Abstract: A method for fabricating a recess pattern in a semiconductor device includes forming a photoresist layer over a substrate including active regions, performing a first photo-exposure process on the photoresist layer using a photo mask including repeatedly formed line structures and spaces, performing a second photo-exposure process on the photoresist layer using a photo mask exposing the active regions, performing a developing process on regions of the photoresist layer whereon both the first and second photo-exposure processes are performed, and etching the substrate to form recess patterns using the remaining photoresist layer.

Abstract: A local skew detecting circuit for a semiconductor integrated circuit includes a reference delay block that receives a test signal and generates a reference delay signal by delaying the test signal by a predetermineddelay time, and a first timing detecting block coupled with the reference delay block, the first timing detecting block configured to receive the test signal, generate a first delay signal by delaying the test signal by the same predetermined delay time, and detect an enable timing order of the reference delay signal and the first delay signal to generate a first detection signal.

Abstract: An apparatus for generating an internal voltage in a semiconductor integrated circuit includes a first voltage generating unit configured to detect a feedback voltage level of a first internal voltage and perform a pumping operation, thereby generating a first internal voltage, and a second voltage generating unit configured to generate a second internal voltage by detecting a feedback voltage level of the second internal voltage, performing level shifting on the detected feedback voltage level, receiving the first internal voltage, and generating the second internal voltage based on the level shifted feedback voltage signal and the received first internal voltage.

Abstract: An operation mode setting apparatus includes an operation mode setting control unit that discriminates the phase of a reference clock from the phase of a feedback clock and generates a locking suspension signal, and an operation mode setting unit that generates a locking completion signal in response to a pulse signal and a phase comparison signal under the control of a reset signal and the locking suspension signal.

Abstract: An address receiving circuit for a semiconductor apparatus includes a controller that, in response to a semiconductor apparatus initialization-related command, generates a control signal having an activation cycle corresponding to the standard of cycle time of the semiconductor apparatus initialization-related command, and an address buffer that receives an address according to the control signal.

Abstract: A DLL circuit can enable a semiconductor integrated circuit to perform a stable data processing operation. The DLL circuit includes a phase splitter that controls the phase of a delay clock, thereby generating a rising clock and a falling clock, an amplifying unit that performs differential amplification on the rising clock and the falling clock in response to first and second duty control signals, thereby generating an amplified rising clock and an amplified falling clock, and a duty cycle control unit that detects the duty rates of the amplified rising clock and the amplified falling clock, thereby generating the first and second duty control signals.

Abstract: A multi-wordline test control circuit in a semiconductor integrated device for performing a multi-wordline test in a specified cell mat among a plurality of cell mats. The multi-wordline test control circuit comprises a multi-test control block for receiving a multi-wordline test signal and outputting a first test signal and a second test signal, and a multi-wordline test block for performing the multi-wordline test in a specified cell mat among a plurality of cell mats in response to the first test signal and the second test signal.

Abstract: A voltage down converter includes a voltage comparator for comparing a first reference voltage and an internal voltage to provide a first driving signal; a driving signal controller coupled with the voltage comparator, the driving signal controller configured to generate a second driving signal in response to an external voltage and selectively providing any one of the first and second driving signals; and a voltage supply coupled with the driving signal controller, the voltage supply configured to receive the selectively provided first and second driving signals, wherein the voltage supply is activated in accordance with the first or second driving signal, thereby providing the internal voltage.

Abstract: A clock signal distribution circuit comprises a voltage control and distribution circuit configured to change a delay of a received clock signal in response to a control voltage and to generate a distributed clock signal, and control voltage generation circuit configured to generate the control voltage using a phase difference between received data and the distributed clock signal.

Abstract: A voltage measuring apparatus for a semiconductor integrated circuit includes a first delay unit configured to delay a reference clock in a first region, a second delay unit configured to delay the reference clock in a second region and an analysis unit configured to analyze a difference in voltage level between the regions based on the phases of associated with the delayed clock signals generated by the first and second delay units.

Abstract: An active driver control circuit for a semiconductor memory apparatus includes an asynchronous decoding unit that can be activated in response to a bank selection signal, when an external command is a read or write command, can generate an enabled read/write enable signal, and when a precharge signal is enabled, disable the enabled read/write enable signal, a synchronous decoding unit that can be activated in response to the bank selection signal, can generate an enabled active enable signal when the external command is an active command, when the external command is a precharge command, can generate the precharge signal, and output the active enable signal and the precharge signal in synchronization with a clock, and an active driver control signal generating unit that can generate an active driver control signal in response to the active enable signal and the read/write enable signal.

Abstract: A semiconductor integrated circuit includes an ODT signal generator that receives an ODT command signal, an ODT reset signal, and an ODT calibration end signal to generate an ODT control signal according to the phase of the ODT calibration end signal, and an ODT resistance adjusting unit that is to perform an on-die termination operation in response to the ODT control signal.

Abstract: A semiconductor memory system which can integrate a plurality of ranks without occupying an increased area. The semiconductor memory system includes a memory device that has a plurality of ranks each having banks integrated therein, and a shared circuit section that is integrated in the memory device and is shared by the plurality of ranks. The plurality of ranks are selectively operated based on the signals provided from the shared circuit section.

Abstract: A circuit for generating an output enable signal in a semiconductor memory apparatus which can include an interval setting unit capable of delaying a burst length signal in synchronized with a clock, thereby generating an interval setting signal, and a signal generating unit for generating an output enable signal in response to a read command signal and the interval setting signal.

Abstract: A data error measuring circuit for a semiconductor memory apparatus includes a data error correction unit that compares data with parity data to correct data, a data selection unit that outputs the data or the corrected data as selected data in response to a test selection signal, and a test result output unit that receives the selected data and the parity data to output a test result signal in response to the test selection signal.

Abstract: A column address decoding circuit of a semiconductor memory apparatus includes a predecoder configured to combine a column address and a decoding test signal, thereby outputting a decoding address. A main decoder receives the decoding address, thereby outputting a plurality of column select signals.

Abstract: A signal receiver circuit includes a first level detector for offset-controlling a first output node in response to a pair of first reference signals. A second level detector offset-controls a second output node in response to a pair of second reference signals.