Abstract: An apparatus for setting an operation mode in a DLL circuit generates a locking completion signal according to a level of a phase comparing signal obtained by comparing phases of a reference clock and a feedback clock. During three or more cycles of a pulse signal, it is determined whether a logic value of levels of the phase comparing signal is a specific combination, and the locking completion signal is selectively enabled.
Type:
Application
Filed:
July 5, 2007
Publication date:
May 15, 2008
Applicant:
Hynx Semiconductor Inc.
Inventors:
Won Joo Yun, Hyun Woo Lee, Nak Kyu Park