Abstract: A method, apparatus and computer-readable storage medium for regulating packet flow through a device such as a router with a switch fabric. Congestion information, such as statistics on bandwidth utilization, is collected for each of a plurality of queues at an egress stage of the device. Based on the bandwidth utilization statistics, computations are performed to evaluate a “discard probability” for each queue. This information is transmitted to the ingress stage, either periodically or at other controlled time periods, such as when the discard probability changes significantly. The ingress stage can then proceed with controllable transmission or non-transmission of packets to the switch fabric, depending on the queue for which the packet is destined and also depending on the discard probability for that queue. In this way, congestion can be avoided even before it even has a chance to occur.

Abstract: Methods and apparatus for processing a plurality of sets of routing information received from corresponding ones of a plurality of neighbor nodes connectable to a router, the router having a plurality of memory units accessible via separate paths. The method comprises creating a respective plurality of non-identical routing information subsets from each of at least one of the received sets of routing information; accessing the plurality of memory units via the separate access paths; and storing the plurality of non-identical routing information subsets created from a given one of said received sets of routing information in respective ones of the plurality of memory units. By providing a distributed memory architecture for storing routing information, an increase in a router's memory requirements can be met by increasing the number of memory units.

Abstract: A communications bus enables communication of data signals in a parallel processing system having a plurality of substantially identical cells, each cell having an access point for transmitting data signals into the communications bus. The communications bus includes a plurality of parallel channels, and at least one channel crossover point associated with each cell. Each crossover point implements a regular change in a channel order of the communications bus, such that each access point is coupled to a channel of the communications bus. Propagation delays are reduced by inserting buffers at regular intervals along the length of each channel. An output buffer at a downstream boundary of each power domain of the system prevents undesired currents due to voltage mismatch. The propagation direction of data signals away from the access point, and propagation of data to an adjacent downstream cell can be controlled to reduce bus traffic and power consumption.

Abstract: A highly robust fault tolerant scan chain is designed for scanning (and/or controlling a configuration of) a parallel processing system. The scan chain implements parallel redundant scan chains that follow physically diverse paths through the parallel processing system. For each IC under test, a set of redundant TAPs perform a boundary scan, and the test results are combined by voting. The TAPs of each set are physically diverse, in that they are physically located in separate power domains of the parallel processing system. As a result, the scan chain is robust to faults affecting power and/or control signal supply to any one power domain. Respective input and output dummy cells at opposite extreme ends of the scan chain provide a graceful separation and recombination of the redundant parallel scan chains, and so renders the architecture of the scan chain transparent to external boundary scan circuit elements.

Abstract: In a method of data transmission according to one embodiment of the invention, data transitions having the same clock dependence are separated in space. In one such method, signals of one set are transmitted on corresponding conductive paths in one direction, signals of another set are transmitted on corresponding conductive paths in the other direction, and adjacent conductive paths that each carry a signal of one set are separated by at least one conductive path that carries a signal of another set. In an apparatus according to one embodiment of the invention, the conductive paths are fabricated on a semiconductor substrate.

Abstract: A reticle and method simultaneously generate small- and large-scale circuit structures of a parallel processing system. The reticle includes at least two circuit traces having respective contact pads within an overlap zone of the reticle. Connectivity between a circuit trace of one reticle image with a circuit trace of an adjacent reticle image is controlled by varying the degree of overlap between the two images.

Abstract: A device and method for deactivating a circuit breaker having an actuating lever and forming part of an electronic module. The electronic module is electrically connected to a power source and is inserted within a housing structure. The deactivating device comprises an activation member moveable between at least two positions, namely activated and deactivated positions, and an interface means for providing a mechanical contact between the activation member and the housing structure. Upon initiating removal of the electronic module from the housing structure for electrical disconnection from the power source, the interface means contacts the activation member to displace the activation member from the activated position to the deactivated position. The activation member in turn contacts the actuating lever to deactivate the circuit breaker thereby ensuring electrical deactivation of the electronic module prior to its electrical disconnection from the power source.

Abstract: A substrate is provided with a plurality of regions, at least one of which is operationally redundant. An integrated circuit to be placed onto the substrate has a plurality of functional units that are designed to be interchangeable. The integrated circuit is tested for defects and, if a functional unit is found to be defective, then the integrated circuit is oriented (e.g., rotated or translated) with respect to the substrate such that the defective functional unit overlies the operationally redundant region of the substrate. A functional association is then formed between the remaining regions of the substrate and the non-defective functional units of the integrated circuit. Such functional association may be achieved by connecting each pair of unit and region. In this way, an integrated circuit with defective functional unit need not be discarded.

Abstract: In a method of data transmission according to one embodiment of the invention, signals on adjacent conductive paths pass through different sequences of inversions and regenerations. In an apparatus according to one embodiment of the invention, two sets of parallel transmission lines include series of inverting and non-inverting buffers having different sequences.

Abstract: The present invention provides a semiconductor wafer that has a predetermined global functionality and comprises a top surface, a bottom surface and a peripheral edge between the top surface and the bottom surface. An integrated circuit is fabricated on the semiconductor wafer and includes a working set of discrete functional modules arranged into a central rectangular array of rows and columns defined by a boundary that includes four rectilinear sides and four corners. The integrated circuit further includes a spare set of discrete functional modules formed outside the boundary of the working set into at least one line that is disposed along a side of the rectangular array of the working set. If a discrete functional module in the working set is found to be defective, it can be replaced by a discrete functional module in the spare set.

Abstract: A data processing system containing a monolithic network of cells with sufficient redundancy provided through direct logical replacement of defective cells by spare cells to allow a large monolithic array of cells without uncorrectable defects to be organized, where the cells have a variety of useful properties. The data processing system according to the present invention overcomes the chip-size limit and off-chip connection bottlenecks of chip-based architectures, the von Neumann bottleneck of uniprocessor architectures, the memory and I/O bottlenecks of parallel processing architectures, and the input bandwidth bottleneck of high-resolution displays, and supports integration of up to an entire massively parallel data processing system into a single monolithic entity.

Abstract: A data processing apparatus, having a first plurality of circuit boards arranged generally side-by-side and a second plurality of circuit boards arranged generally side-by-side, the first plurality of circuit boards being mounted to the second plurality of circuit boards by a midplane. The midplane has a first main surface, a second main surface and a plurality of connector elements, each connector element including an array of electrical couplers that extend generally transversally to the main surfaces of the midplane. The array of electrical couplers connect data contacts on one circuit board mounted to the first surface of the midplane to data contacts of another circuit board mounted to the second surface of the midplane. The connection between the circuit boards is such that each data contact on one circuit board and the corresponding data contact of the other circuit board are in physical contact with a common electrical coupler.

Abstract: A massively parallel data processing system consisting of an array of closely spaced cells where each cell has direct output means as well as means for processing, memory and input. The data processing system according to the present invention overcomes the von Neumann bottleneck of uniprocessor architectures, the I/O and memory bottlenecks that plague parallel processors, and the input bandwidth bottleneck of high-resolution displays.

Abstract: A shelf unit for use in an electronic equipment rack, comprises an electronic equipment structure for holding electronic equipment. An auxiliary equipment structure, such as a fiber management plate, is provided for holding auxiliary equipment. A fan tray is movable in and out of a corresponding tray support structure forming part of the shelf unit. The tray support structure is configured such that when the associated fan tray is pushed in, the fan tray extends in a plane behind the auxiliary equipment structure, but when pulled out the fan tray drops down to clear the auxiliary equipment structure and provide access to the fan in the tray.

Abstract: A PCB insertion and extraction device includes a latching lever carrying a latch adapted to cooperate with a catch to latch the lever in an insertion position thereof. The latch is received in a hole extending through the lever and has an operating end which can be manually operated from a front side of the lever to pivot the latch relative to the lever. The catch is defined in the PCB assembly. A switch is provided in the catch so as to be triggered by the latch when the same is positively engaged with the catch.

Abstract: A data processing system containing a monolithic network of cells with sufficient redundancy provided through direct logical replacement of defective cells by spare cells to allow a large monolithic array of cells without uncorrectable defects to be organized, where the cells have a variety of useful properties. The data processing system according to the present invention overcomes the chip-size limit and off-chip connection bottlenecks of chip-based architectures, the von Neumann bottleneck of uniprocessor architectures, the memory and I/O bottlenecks of parallel processing architectures, and the input bandwidth bottleneck of high-resolution displays, and supports integration of up to an entire massively parallel data processing system into a single monolithic entity.

Abstract: A data processing system containing a monolithic network of cells with sufficient redundancy provided through direct logical replacement of defective cells by spare cells to allow a large monolithic array of cells without uncorrectable defects to by organized, where the cells have a variety of useful properties. The data processing system according to the present invention overcomes the chip-size limit and off-chip connection bottlenecks of chip-based architectures, the von Neumann bottleneck of uniprocessor architectures, the memory and I/O bottlenecks of parallel processing architectures, and the input bandwidth bottleneck of high-resolution displays, and supports integration of up to an entire massively parallel data processing system into single monolithic entity.

Abstract: A data processing system containing a monolithic network of cells with sufficient redundancy provided through direct logical replacement of defective cells by spare cells to allow a large monolithic array of cells without uncorrectable defects to be organized, where the cells have a variety of useful properties. The data processing system according to the present invention overcomes the chip-size limit and off-chip connection bottlenecks of chip-based architectures, the von Neumann bottleneck of uniprocessor architectures, the memory and I/O bottlenecks of parallel processing architectures, and the input bandwidth bottleneck of high-resolution displays, and supports integration of up to an entire massively parallel data processing system into a single monolithic entity.