Abstract: The present invention related to a method for compiling high-level software code into hardware, transforming each instruction into a respective hardware block and using an execution control signal representing the program pointer for triggering the execution within each respective hardware block.

Abstract: The present invention relates to a method for compiling code for a multi-core processor, comprising: detecting and optimizing a loop, partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism, optimizing the loop iterations and/or loop counter for ideal mapping on hardware, chaining the loop partitions generating a list representing the execution sequence of the partitions.

Abstract: The invention relates to a multi-core processor system, in particular a single-package multi-core processor system, comprising at least two processor cores, preferably at least four processor cores, each of said a least two cores, preferably at least four processor core, having a local LEVEL-1 cache, a tree communication structure combining the multiple LEVEL-1 caches, the tree having at 1 a one node, preferably at least three nodes for a four processor. core multi-core processor, and TAG information is associated to data managed within the tree, usable in the treatment of the data.

Abstract: The present invention relates to a method for compiling high-level software code into hardware, transforming each instruction into a respective hardware block and using an execution control signal representing the program pointer for triggering the execution within each respective hardware block.

Abstract: The present invention relates to a method for compiling code for a multi-core processor, comprising: detecting and optimizing a loop, partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism, optimizing the loop iterations and/or loop counter for ideal mapping on hardware, chaining the loop partitions generating a list representing the execution sequence of the partitions.

Abstract: The present invention relates to a processor having a trace cache and a plurality of ALUs arranged in a matrix, comprising an analyser unit located between the trace cache and the ALUs, wherein the analyser unit analyses the code in the trace cache, detects loops, transforms the code, and issues to the ALUs sections of the code combined to blocks for joint execution for a plurality of clock cycles.

Abstract: The present invention relates to a processor having a trace cache and a plurality of ALUs arranged in a matrix, comprising an analyzer unit located between the trace cache and the ALUs, wherein the analyzer unit analyzes the code in the trace cache, detects loops, transforms the code, and issues to the ALUs sections of the code combined to blocks for joint execution for a plurality of clock cycles.

Abstract: The present invention discloses a single chip sequential processor comprising at least one ALU-Block wherein said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.

Abstract: The invention relates to a multi-core processor system, in particular a single-package multi-core processor system, comprising at least two processor cores, preferably at least four processor cores, each of said a least two cores, preferably at least four processor core, having a local LEVEL-1 cache, a tree communication structure combining the multiple LEVEL-1 caches, the tree having at 1 a one node, preferably at least three nodes for a four processor. core multi-core processor, and TAG information is associated to data managed within the tree, usable in the treatment of the data.

Abstract: The present invention relates to a method for compiling code for a multi-core processor, comprising: detecting and optimizing a loop, partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism, optimizing the loop iterations and/or loop counter for ideal mapping on hardware, chaining the loop partitions generating a list representing the execution sequence of the partitions.

Abstract: The present invention discloses a single chip sequential processor comprising at least one ALU-Block wherein said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.

Abstract: The invention relates to a multi-core processor system, in particular a single-package multi-core processor system, comprising at least two processor cores, preferably at least four processor cores, each of said at least two cores, preferably at least four processor cores, having a local LEVEL-1 cache, a tree communication structure combining the multiple LEVEL-1 caches, the tree having at least one node, preferably at least three nodes for a four processor core multi-core processor, and TAG information is associated to data managed within the tree, usable in the treatment of the data.

Abstract: The present invention relates to a method for compiling code for a multi-core processor, comprising: detecting and optimizing a loop, partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism, optimizing the loop iterations and/or loop counter for ideal mapping on hardware, chaining the loop partitions generating a list representing the execution sequence of the partitions.

Abstract: The present invention relates to a processor core having an execution unit comprising an arrangement of Arithmetic-Logic-Units, wherein the operation mode of the execution unit is switchable between an asynchronous operation of the Arithmetic-Logic-Units and interconnection between the Arithmetic-Logic-Units such that a signal. from the register file crosses the execution unit and is receipt by the register file in one clock cycle; and wherein a pipelined operation mode of at least one of the Arithmetic-Logic-Units and the interconnection between the Arithmetic-Logic-Units such that a signal requires from the register file through the execution unit back to the register file more than one clock cycles.

Abstract: The present invention relates to a method for compiling high-level software code into hardware, transforming each instruction into a respective hardware block and using an execution control signal representing the program pointer for triggering the execution within each respective hardware block.

Abstract: The present invention relates to a method for compiling code for a multi-core processor, comprising: detecting and optimizing a loop, partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism, optimizing the loop iterations and/or loop counter for ideal mapping on hardware, chaining the loop partitions generating a list representing the execution sequence of the partitions.

Abstract: The present invention discloses a single chip sequential processor comprising at least one ALU-Block wherein said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.

Abstract: The invention relates to a multi-core processor system, in particular a single-package multi-core processor system, comprising at least two processor cores, preferably at least four processor cores, each of said at least two cores, preferably at least four processor cores, having a local LEVEL-1 cache, a tree communication structure combining the multiple LEVEL-1 caches, the tree having at least one node, preferably at least three nodes for a four processor core multi-core processor, and TAG information is associated to data managed within the tree, usable in the treatment of the data.