Abstract: The present disclosure relates to error correction coding based on generalized concatenated codes with restricted error values for code-based cryptography. The error correction encoding comprises encoding the information according to a McEliece cryptosystem or according to a Niederreiter cryptosystem, in each case using an error vector containing at most t ? non-zero error values; and a combination of: a permutation operation, a scrambling operation; and a coding operation involving a p-ary generalized concatenated code, GCC, having an error correction capability t up to which it can correct all possible error patterns. The GCC comprises multiple outer codes A(1) with different dimensions n1 and 1=0, . . .

Abstract: Systems and methods are provided for optimizing an access scheme for memory accesses by a host to a data memory managed by a memory controller with one or more memory media. An access scenario communicated by the host is received by the memory controller, An optimized access scheme is determined that defines a specific sequence of physical memory accesses to the data memory to be executed by the memory controller to implement the access scenario. The optimization shortens a total access time for the access scenario, by modifying a memory access by means of a shift of a respective physical memory area to be addressed thereby in relation to an address mapping and/or by means of a temporal advancement of the respective memory access. Access information defining the optimized access scheme is then stored to allow it to subsequently be automatically executed in response to a call.

Abstract: A method for read reference voltage calibration of a non-volatile memory, NVM, such as flash memory, particularly of the NAND type, comprises: Reading from the NVM predetermined reference data stored therein and being encoded with an error correction code, ECC, wherein the reading is performed when a read reference voltage of the NVM, which is used as a reference voltage, such as a threshold voltage, for the reading, is set at a defined voltage level; decoding the read data and observing a number of bit errors, e.g., in a codeword, of the read data in relation to the reference data; and defining a new voltage level of the read reference voltage for a subsequent reading of data from the NVM based on the observed number of bit errors and setting the read reference voltage to the defined new voltage level.

Abstract: Systems and methods are provided for optimizing an access scheme for memory accesses by a host to a data memory managed by a memory controller with one or more memory media. An access scenario communicated by the host is received by the memory controller, An optimized access scheme is determined that defines a specific sequence of physical memory accesses to the data memory to be executed by the memory controller to implement the access scenario. The optimization shortens a total access time for the access scenario, by modifying a memory access by means of a shift of a respective physical memory area to be addressed thereby in relation to an address mapping and/or by means of a temporal advancement of the respective memory access. Access information defining the optimized access scheme is then stored to allow it to subsequently be automatically executed in response to a call.

Abstract: Provided is a method and a data processing apparatus for restructuring input data to be stored in a flash memory having a plurality of multi-level flash memory cells. The method comprises: based on a defined page structure according to which the input data is segmented into multiple logical input pages, restructuring the segmented input data to obtain corresponding output data being segmented into logical output pages, wherein each output page has one or more associated destination data pages for storing content of the output page therein; and outputting the segmented output data for storage to the flash memory in accordance with the associations between the output pages and their respective destination data pages. The restructuring comprises assigning to each output page a respective corresponding input page, and selecting the respective input page for assignment to the respective output page.

Abstract: Some embodiments relate to a method and a corresponding apparatus for estimating the wear of a non-volatile memory. Such a method may include determining a load profile with respect to a real access load occurring during a defined test period where the load profile indicates a respectively associated access load for accesses to a first NVM, and generating access data representing the determined load profile. The method further includes determining an estimated value for the wear of a particular second NVM in part on the basis of the access data.

Abstract: The invention relates to a soft input decoding method and a decoder for generalized concatenated (GC) codes. The GC codes are constructed from inner nested block codes, such as binary Bose-Chaudhuri-Hocquenghem, BCH, codes and outer codes, such as Reed-Solomon, RS, codes. In order to enable soft input decoding for the inner block codes, a sequential stack decoding algorithm is used. Ordinary stack decoding of binary block codes requires the complete trellis of the code. In one aspect, the present invention applies instead a representation of the block codes based on the trellises of supercodes in order to reduce the memory requirements for the representation of the inner codes. This enables an efficient hardware implementation. In another aspect, the present invention provides a soft input decoding method and device employing a sequential stack decoding algorithm in combination with list-of-two decoding which is particularly well suited for applications that require very low residual error rates.

Abstract: Field error correction coding is particularly suitable for applications in non-volatile flash memories. We describe a method for error correction encoding of data to be stored in a memory device, a corresponding method for decoding a codeword matrix resulting from the encoding method, a coding device, and a computer program for performing the methods on the coding device, using a new construction for high-rate generalized concatenated (GC) codes. The codes, which are well suited for error correction in flash memories for high reliability data storage, are constructed from inner nested binary Bose-Chaudhuri-Hocquenghem (BCH) codes and outer codes, preferably Reed-Solomon (RS) codes. For the inner codes extended BCH codes are used, where only single parity-check codes are applied in the first level of the GC code. This enables high-rate codes.

Abstract: Various embodiments are related to non-volatile memories, systems, and methods of using such. Some such embodiments include a memory controller that is configured to reserve a predetermined amount of unused dedicated memory in the NVM and control the memory system to operate in a normal mode of operation in which it is configured to provide at least write access to the NVM, enable a garbage collection process for the NVM, and maintain in the NVM at least said amount of dedicated unused memory. Reserving the predetermined amount of unused dedicated memory in the NVM and controlling the memory system to operate in the normal mode of operation includes reserving at least one specific unused dedicated memory portion in the NVM and controlling the memory system such that during the normal mode of operation the host's write access to the dedicated memory portion is disabled.

Abstract: Field error correction coding is particularly suitable for applications in non-volatile flash memories. We describe a method for error correction encoding of data to be stored in a memory device, a corresponding method for decoding a codeword matrix resulting from the encoding method, a coding device, and a computer program for performing the methods on the coding device, using a new construction for high-rate generalized concatenated (GC) codes. The codes, which are well suited for error correction in flash memories for high reliability data storage, are constructed from inner nested binary Bose-Chaudhuri-Hocquenghem (BCH) codes and outer codes, preferably Reed-Solomon (RS) codes. For the inner codes extended BCH codes are used, where only single parity-check codes are applied in the first level of the GC code. This enables high-rate codes.

Abstract: Various embodiments are related to non-volatile memories, systems, and methods of using such. Some instances provide a computer readable medium that includes instructions executable by one or more processors of an NVM controller for controlling a NVM using memory pages where the NVM controller having a predefined error correction coding, ECC, capability (ECCCTRL). Executing the instructions may cause the NVM controller to: perform a monitoring process and perform a transitioning process.

Abstract: A method renews data in a flash memory which is organized in memory units and whose memory units which have been written to are error-protected using ECC words. The memory units which have been written to are test-read in regularly activated test-reading cycles, and either individual memory units which have been written to or all memory units which have been written to are renewed on the basis of the ECC error states which have occurred in a test-reading cycle.

Abstract: Extended commands are transmitted from computer system via a standard interface to a memory system. The computer system accesses logical memory addresses via an application interface using standard read/write commands which are processed by a memory controller in the memory system. A sequence of read commands for at least two logical memory addresses with address values that differ in at least one bit are output by the computer system. The memory controller compares the sequence of different bits with a predefined bit sequence, the magical address sequence. In the event of a match, a subsequent write command for one of the logical memory addresses is used to open a management connection between the computer system and the memory controller, and the useful data contained in the write command are evaluated by the memory controller and are not written to the addressed memory address.

Abstract: A flash memory for a host system has a multiplicity of memory blocks. The memory blocks are subdivided into memory pages which can be written to and each memory page are also subdivided into partial pages and each partial page having a physical partial page address which is assigned a logical partial page address which can be addressed. The physical partial page addresses assigned to the logical partial page addresses are able to be determined using hierarchically organized structures of address tables for converting logical partial page addresses into physical partial page addresses. The multiplicity of memory blocks of the flash memory are divided into areas which comprise at least one static area of memory blocks which have been written to, a write area to which new and changed useful data are written, a block management area which stores management data for the memory blocks, and a logbook area.

Abstract: A method manages a flash memory for a computer system having flash chips divided into separately erasable physical memory blocks with a limited maximum erasure frequency. The memory blocks are divided into writable pages being subdivided into addressable subpages. The subpages are addressed by a computer via logical sector addresses being converted into physical subpage addresses. The flash memory has a first area containing single-level flash chips with a higher maximum erasure frequency, and a second area containing multi-level flash chips with a lower maximum erasure frequency. If write operations in the first area exceed an upper threshold for a filling level of written memory blocks, a written memory block having a low erasure counter is searched for in the first area, whose valid subpages are transferred into a memory block of the second area. The address allocations for the transferred subpages are updated.

Abstract: Data bits are programmed in cells of a flash memory which is divided into a multiplicity of separately erasable physical blocks, which are in turn split into individual physical pages to which the data bits can be written. The data bits are held in multilevel cells that store one lower bit and one upper bit per cell. The four states of which are distinguished by three voltage threshold values. The lower states are associated with the lower bit and the upper states are associated with the upper bit. The pages are distinguished by lower pages allocated to the lower bits, and upper pages allocated to the upper bits. Lower and upper pages which contain the same cells are combined by a pairing table to form paired pages. Reliable storage of data bits is achieved by programming paired pages with the same data bits and listing them as reliable paired pages in management data for the flash memory.

Abstract: A method manages a flash memory having a plurality of physical blocks. The blocks of the memory are addressed by logic block addresses which are converted into physical block addresses. In each block a deletion counter is run in which the number of deletions of the block is counted, and two regions having different types of flash chips are present. A first region contains single-level flash chips with a large maximum deletion frequency, and a second region contains multi-level flash chips with a lower maximum deletion frequency. When writing to the memory the address conversion of the logic addresses into physical addresses is carried out such that all blocks of the first region are written, when all blocks of the first region have been written and a further writing process is initiated, the block in the first region having the lowest deletion counter is copied into a blank block in the second region.

Abstract: An apparatus and a method for correcting data errors in a data block. The data block contains original data which are supplemented by such a security syndrome that the data block effects a correction of at most t data errors, wherein a parallel-operating quick corrector is used. The quick corrector is only designed for a correction of a subset t1 of the set of the at most t data errors, and the quick corrector includes a test encoder, which sets a first test state flag P1 which, in the event of a complete correction of a processed data block, outputs this data block and secondly activates a series-operating post-corrector for at most t data errors. The output signal of the post-corrector is output as an alternative.

Abstract: A method for addressing a memory having a plurality of flash memory chips organized in erasable blocks, which in turn contain writable sectors, and where an erase counter is associated with each memory block. The overwriting of the sectors occurs by way of alternative memory blocks searched in the same chip for low erase counter values, as long as a threshold value of the erase counter is not exceeded. The copying operations are conducted efficiently using a copy command internal to the memory chip. As soon as the threshold value is exceeded, alternative memory blocks are searched in other memory chips as well.

Abstract: A method manages a flash memory having a plurality of physical blocks. The blocks of the memory are addressed by logic block addresses which are converted into physical block addresses. In each block a deletion counter is run in which the number of deletions of the block is counted, and two regions having different types of flash chips are present. A first region contains single-level flash chips with a large maximum deletion frequency, and a second region contains multi-level flash chips with a lower maximum deletion frequency. When writing to the memory the address conversion of the logic addresses into physical addresses is carried out such that all blocks of the first region are written, when all blocks of the first region have been written and a further writing process is initiated, the block in the first region having the lowest deletion counter is copied into a blank block in the second region.