Abstract: Systems and methods are provided for optimizing an access scheme for memory accesses by a host to a data memory managed by a memory controller with one or more memory media. An access scenario communicated by the host is received by the memory controller, An optimized access scheme is determined that defines a specific sequence of physical memory accesses to the data memory to be executed by the memory controller to implement the access scenario. The optimization shortens a total access time for the access scenario, by modifying a memory access by means of a shift of a respective physical memory area to be addressed thereby in relation to an address mapping and/or by means of a temporal advancement of the respective memory access. Access information defining the optimized access scheme is then stored to allow it to subsequently be automatically executed in response to a call.

Abstract: Provided is a method and a data processing apparatus for restructuring input data to be stored in a flash memory having a plurality of multi-level flash memory cells. The method comprises: based on a defined page structure according to which the input data is segmented into multiple logical input pages, restructuring the segmented input data to obtain corresponding output data being segmented into logical output pages, wherein each output page has one or more associated destination data pages for storing content of the output page therein; and outputting the segmented output data for storage to the flash memory in accordance with the associations between the output pages and their respective destination data pages. The restructuring comprises assigning to each output page a respective corresponding input page, and selecting the respective input page for assignment to the respective output page.

Abstract: Various embodiments are related to non-volatile memories, systems, and methods of using such. Some instances provide a computer readable medium that includes instructions executable by one or more processors of an NVM controller for controlling a NVM using memory pages where the NVM controller having a predefined error correction coding, ECC, capability (ECCCTRL). Executing the instructions may cause the NVM controller to: perform a monitoring process and perform a transitioning process.

Abstract: A method renews data in a flash memory which is organized in memory units and whose memory units which have been written to are error-protected using ECC words. The memory units which have been written to are test-read in regularly activated test-reading cycles, and either individual memory units which have been written to or all memory units which have been written to are renewed on the basis of the ECC error states which have occurred in a test-reading cycle.

Abstract: Extended commands are transmitted from computer system via a standard interface to a memory system. The computer system accesses logical memory addresses via an application interface using standard read/write commands which are processed by a memory controller in the memory system. A sequence of read commands for at least two logical memory addresses with address values that differ in at least one bit are output by the computer system. The memory controller compares the sequence of different bits with a predefined bit sequence, the magical address sequence. In the event of a match, a subsequent write command for one of the logical memory addresses is used to open a management connection between the computer system and the memory controller, and the useful data contained in the write command are evaluated by the memory controller and are not written to the addressed memory address.

Abstract: A flash memory for a host system has a multiplicity of memory blocks. The memory blocks are subdivided into memory pages which can be written to and each memory page are also subdivided into partial pages and each partial page having a physical partial page address which is assigned a logical partial page address which can be addressed. The physical partial page addresses assigned to the logical partial page addresses are able to be determined using hierarchically organized structures of address tables for converting logical partial page addresses into physical partial page addresses. The multiplicity of memory blocks of the flash memory are divided into areas which comprise at least one static area of memory blocks which have been written to, a write area to which new and changed useful data are written, a block management area which stores management data for the memory blocks, and a logbook area.

Abstract: Data bits are programmed in cells of a flash memory which is divided into a multiplicity of separately erasable physical blocks, which are in turn split into individual physical pages to which the data bits can be written. The data bits are held in multilevel cells that store one lower bit and one upper bit per cell. The four states of which are distinguished by three voltage threshold values. The lower states are associated with the lower bit and the upper states are associated with the upper bit. The pages are distinguished by lower pages allocated to the lower bits, and upper pages allocated to the upper bits. Lower and upper pages which contain the same cells are combined by a pairing table to form paired pages. Reliable storage of data bits is achieved by programming paired pages with the same data bits and listing them as reliable paired pages in management data for the flash memory.

Abstract: A method manages a flash memory having a plurality of physical blocks. The blocks of the memory are addressed by logic block addresses which are converted into physical block addresses. In each block a deletion counter is run in which the number of deletions of the block is counted, and two regions having different types of flash chips are present. A first region contains single-level flash chips with a large maximum deletion frequency, and a second region contains multi-level flash chips with a lower maximum deletion frequency. When writing to the memory the address conversion of the logic addresses into physical addresses is carried out such that all blocks of the first region are written, when all blocks of the first region have been written and a further writing process is initiated, the block in the first region having the lowest deletion counter is copied into a blank block in the second region.

Abstract: A method for addressing a memory having a plurality of flash memory chips organized in erasable blocks, which in turn contain writable sectors, and where an erase counter is associated with each memory block. The overwriting of the sectors occurs by way of alternative memory blocks searched in the same chip for low erase counter values, as long as a threshold value of the erase counter is not exceeded. The copying operations are conducted efficiently using a copy command internal to the memory chip. As soon as the threshold value is exceeded, alternative memory blocks are searched in other memory chips as well.

Abstract: The invention relates to a memory system which is connected to a host system by means of a host bus (HB). Said system contains a memory controller (FC) having an internal memory (IR) and flash memory chips (F1 . . . Fn) which are organised in individually deletable memory blocks. Said blocks contain a plurality of writeable and readable memory sectors, and the sectors are divided into sector sections which are secured by an ECC-word. The sectors are temporarily stored in the alternating sector buffers (SB1, SB2) in order to communicate with the host system and are transmitted between the sector buffers (SB1, SB2) and the flash memory chips (F1 . . . Fn), by means of a direct-flash-access-unit (DFA), without having to be temporarily stored in the internal memory (IR) of the memory controller (FC).

Abstract: A method for addressing memory pages of a non-volatile memory in a memory system with a memory controller and a further volatile memory. The non-volatile memory is organized in erasable memory blocks with a multiplicity of memory pages, and each memory page, containing a number of sectors, can be written individually. The volatile memory holds an address translation table specifying an assignment of logical memory page addresses to physical memory page addresses. By way of the memory controller, a reconstruction table is stored as a copy of the address translation table in one or more memory blocks in the non-volatile memory, a log book table with data records containing changed assignments of logical memory page addresses to physical memory page addresses, is carried in the volatile memory and, if the log book table exceeds a predetermined size, a changed reconstruction table is stored in the non-volatile memory.

Abstract: A memory system is provided which is configured with a plurality of memory controllers (SCx), disposed in parallel on a clocked bus (B), and memory chips (Fx) associated with the respective memory controllers (SCx). The system communicates via the bus (B) with a host system (HS) by operational memory commands that use logical memory sector numbers. The inventive system is characterized by an arbitration among the memory controllers so that for any memory operation requested by the host system (HS) the memory controller affected with respect to a range of logical memory sector numbers takes over the bus for communication with the host system.