Abstract: A land grid array (LGA) type semiconductor chip package includes an insulation body having a plurality of first conductive interconnections embedded therein. A cavity is formed in an upper portion of the insulation body. A plurality of first conductive interconnection patterns is formed outside the cavity and on marginal upper surfaces of the insulation body, and a plurality of second conductive interconnection patterns is formed on marginal lower surfaces of the insulation body. A plurality of third conductive interconnection patterns electrically connects the first and second conductive interconnection patterns, and a plurality of conductive bond pads is formed on a bottom of the cavity. A semiconductor chip is attached on the respective bond pads by a first adhesive member and a heat discharge member is attached by a second adhesive member on an upper surface of the semiconductor chip. An epoxy molding compound fills the cavity.

Abstract: A method for testing an overlay occurring in a semiconductor device to compensate for an error generated in the measurement of overlay. This method involves forming an inner mark on a semiconductor wafer, and forming an outer mark on the semiconductor wafer in such a fashion that the outer mark is inclined in one direction and has an island portion arranged in the inside of the inner mark and a land portion comprised of a photoresist film pattern formed over the entire surface of the semiconductor wafer while being spaced from the island portion by a desired distance, thereby forming an overlay measuring mark consisting of the inner and outer marks. Measured values of the island and land portions of the inner mark are averaged and then compared with measured values of the outer mark, thereby deriving overlay compensation values. Accordingly, even if the overlay measuring mark is formed in an inclined state, the method can simply measure an inaccuracy in measured overlay value.