Abstract: A method for forming a multilayer metal thin film capable of improving electromigration reliability. The method includes steps of forming a Ti film having an <002> crystal orientation by using an ionized physical vapor deposition method, forming a TiN film on the Ti film in order to form a multilayer stack, wherein the TiN film has an <111> crystal orientation, and forming an aluminum film on the multilayer stack in an <111> crystal orientation. Accordingly, the aluminum metal interconnection increases the <002> orientation of the Ti film and improves the <111> orientation of the aluminum to control electromigration resistance, by using the IPVD method in forming the Ti film as an underlayer of the aluminum film.

Abstract: A backward closed loop power control apparatus for a mobile communication system is disclosed.

Abstract: A semiconductor chip package and a fabrication method thereof can reduce fabrication time and cost by consecutively fabricating a semiconductor chip to the package at a wafer level. The method for fabricating the semiconductor chip package includes a step of forming the semiconductor chip having a plurality of pads at its upper portion on a wafer, a step of forming a low elastic modulus material layer 22, such as a silicone on the wafer except the pads by a spin coating process or a sputtering process, a step of forming metal patterns on the pads and the low elastic modulus material layer by a metal thin film deposition process or a photo lithography process, a step of forming a high elastic modulus material layer on the metal patterns and the low elastic modulus material layer, a step of partially exposing the upper portions of the metal patterns, and a step of boding electric media to the exposed metal patterns.

Abstract: A nonvolatile memory device includes: a first insulating film, a selection gate, a second insulating film and an erase gate layered on a semiconductor substrate; sidewalls formed in contact with both sides of the selection gate, the erase gate and the second insulating film; a third insulating film formed over an upper surface and an edge of the erase gate; a fourth insulating film formed on the surface of the semiconductor substrate in contact with the sidewalls; a floating gate overlapping the erase gate at a certain width; a dielectric film formed on the floating gate; a source/drain formed in the semiconductor below the floating gate and one of the sidewalls; and a control gate formed on the entire surface including the erase and floating gate.

Abstract: A stackable Ball Grid Array (BGA) semiconductor chip package and a fabrication method thereof increases reliability and mount density of a semiconductor package. The stackable BGA semiconductor chip package includes a supporting member that includes a supporting plate and a supporting frame formed on edges of the supporting plate. Conductive patterns are formed in and extend through the supporting member. First metal traces are formed on a bottom of the supporting plate and the first metal traces are connected to first ends of the conductive patterns in the supporting member. Second metal traces are attached to an upper surface of a semiconductor chip, and the semiconductor chip is attached to the supporting member. The second metal traces are connected to bond pads of the chip, and to upper ends of the conductive patterns in the supporting member. A plurality of conductive balls are then attached to exposed portions of the first and/or the second metal traces.

Abstract: A data bus line control circuit prevents a problem of a data access operation on a global data bus (GDB) line although two blocks are simultaneously selected. The data bus line control circuit includes: a global data bus line which is arranged between memory units adjacent to each other as two pairs, and transmits a data from a local data bus line positioned between adjacent sub blocks; and transmission means which is connected between the local data bus line and the global data bus line, and transmits bit line signals of two sub blocks to one pair of global data bus lines different from each other through the local data bus line, when the two sub blocks are simultaneously selected by a block isolation selection signal. As a result, a circuit arrangement and a layout design become simplified, and two operations of 8K refresh and 4K refresh are possible in one chip, therefore, two kinds of effects can be achieved by one chip.

Abstract: A semiconductor device with an electrostatic discharge (ESD) protective circuit is disclosed. In this semiconductor device with an ESD protective circuit, an n-well guard ring is formed around an NMOS field transistor of a data input buffer or around an NMOS transistor of a data output buffer. The n-well guard ring is strapped to an n-well of a PMOS field transistor and to an n-well of a PMOS transistor, and thus a PNPN path is formed toward the PMOS transistor at a positive mode of the ground voltage. Therefore, the electrical resistance between the wells of the NMOS transistors and the PMOS transistors can be reduced, thereby improving the characteristics of the ESD protective circuit and a latch-up device. Further the layout area is reduced, and thus, the characteristics and the reliability of the semiconductor device are improved.

Abstract: The present invention relates to a power on reset circuit capable of stabilizing an operation of a chip by generating a reset signal regardless of a ramp up time of a power supply voltage, and includes a first means for controlling a potential of a first node to a first potential according to a potential of a second node, a second means for supplying the power supply voltage to be ramped up to the second node according to the potential of the first node, a third means for determining a potential of a third node by inverting and delaying the potential of the second node, a fourth means for controlling a potential of a fourth node to a second potential according to the potential of the third node, a fifth means for inverting and delaying the potential of the fourth node, a sixth means for outputting the potential of the third node to an output terminal according to an output signal from said fifth means and its inverted signal, and a seventh means for controlling a signal of the output terminal according to the

Abstract: A stackable Ball Grid Array (BGA) semiconductor chip package and a fabrication method thereof increases reliability and mount density of a semiconductor package. The stackable BGA semiconductor chip package includes a supporting member that includes a supporting plate and a supporting frame formed on edges of the supporting plate. Conductive patterns are formed in and extend through the supporting member. First metal traces are formed on a bottom of the supporting plate and the first metal traces are connected to first ends of the conductive patterns in the supporting member. Second metal traces are attached to an upper surface of a semiconductor chip, and the semiconductor chip is attached to the supporting member. The second metal traces are connected to bond pads of the chip, and to upper ends of the conductive patterns in the supporting member. A plurality of conductive balls are then attached to exposed portions of the first and/or the second metal traces.

Abstract: An improved framing identification and timing signal extraction apparatus for a very small aperture terminal system and a method thereof, which includes a clock signal divider for dividing a clock signal inputted and an inverter delay clock signal into a predetermined number of signals, generating a dividing signal having a different frequency, and an output enable signal and a write enable signal, a first memory for storing and outputting a predetermined data by using one dividing signal among the dividing signals outputted from the clock divider as its address signal, a second memory for receiving the output signal from the first memory and the divider as an address signal, converting the state by using the received address signal, and outputting a corresponding state value, and a control logic unit for extracting a control signal and a framing identification and timing (FIT) data in accordance with the output from the second memory and the control signal from the divider.

Abstract: A method for forming an element isolating film of a semiconductor device, which is capable of achieving a reduction in topology and a reduction in the occurrence of a bird's beak phenomenon, so that subsequent processes can be easily carried out to fabricate highly integrated semiconductor devices.

Abstract: A memory device for storing multi-data comprises an input level detector for receiving data through n input terminals and selecting one of 2.sup.n output terminals corresponding to the data inputted to the input terminals; a word line switching unit for outputting one of 2.sup.n reference voltages corresponding to the outputs from the input level detector; and a word line driver for receiving the output from the word line switching unit and transferring it to the corresponding word line of the memory device.

Abstract: An improved telephone test device and a method of the same for an optical cable television which are capable of easily testing a telephone function of an optical cable television system by connecting to the subscriber's line of the optical cable television system without using an additional switch system, which includes the steps of a first step for initializing a database, selecting a predetermined bus, Cept interface boards-10, and a hardware, executing a menu, and judging the inputted menu; a second step for performing an extended common control board assembly loop-back test routine when the extended common control board assembly is selected in the first step for testing the extended common control board assembly loop-back; a third step for performing Cept interface boards-10 loop-back test routine when the loop-back is selected in the first step for performing the Cept interface boards-10 loop-back; a fourth step for performing a common test routine when the common test is selected in the first step; a fi

Abstract: Disclosed is the FIFO buffer memory, comprising a core memory 12 having a dual port structure, for substantially storing data, first and second address decoders 13 and 14 responsive to read and write clock signals, for producing addresses indicative of directing locations in the core memory when data is written in the core memory or when the data is read from the core memory, and a status detector 15 for generating memory status signals indicating whether the data can be written in the FIFO buffer memory or whether the data can be read from the FIFO buffer memory, i.e. full and empty flags. The buffer memory can be embodied without use of complicated circuits such as address counter, address register and comparator, which can be operated at high speed and embodied with high-density integration.

Abstract: A data output buffer for a semiconductor memory device having a plurality of memory cells, each of the memory cells storing a data signal. The data output buffer comprises: an input line for inputting the data signal from each of the memory cells; a pull-up driver connected between a supply voltage source and an output line, the pull-up driver being driven in response to a first logic of the data signal from the input line; a pull-down driver connected between a ground voltage source and the output line, the pull-down driver being driven complementarily to the pull-up driver in response to a second logic of the data signal from the input line; at least one auxiliary pull-up driver connected in parallel to the pull-up driver; and a controller for driving the at least one auxiliary pull-up driver for a predetermined time period from a start portion of the first logic of the data signal from the input line.

Abstract: A circuit for generating a column decoder enable signal in a semiconductor device, capable of transmitting data on bit lines toward data bus lines at an optimum point in time, even when the fabrication process, the supply voltage, and the temperature used are varied. The circuit includes true and complementary dummy bit lines constructed in a normal cell array, each of the dummy bit lines including dummy cells, and a dummy bit line sensing amplifier connected to the true and complementary dummy bit lines and adapted to generate a column decoder enable signal using data from the true and complementary dummy bit lines.

Abstract: A common control redundancy switch method capable of, when an error occurs at an active common control unit, replacing the card at which the error occurs by a spare card, thereby performing operations as usual without affecting the overall network and, thus, reducing the time taken for repair during the stop of the system caused by the error. When a local control task of an active common control unit receives a switch message from a network management system via a configuration control task, it discriminates whether an inactive common control unit is at a switchover enable state. Upon receiving the switch message, an inactive common control unit transmits a response message to the switch message to a local control task of the active common control unit. When the local control task of the active common control unit receives the response message, a performance monitor gives a hardware initiated alarm informing of the initiation of the switchover routine.

Abstract: A storage electrode of a DRAM cell in a highly-integrated semiconductor device has, in order to secure the surface area thereof greater than that of a conventional tunnel-type storage electrode, an upper plate of storage electrode formed over a lower plate of storage electrode separated therefrom by a predetermined distance, while interposing bars of various shapes formed of a conductive layer to electrically connect the upper and lower plates, and a method for manufacturing the storage electrode is also provided.