Abstract: A flash EEPROM array having a double-diffused source junction that can be used for source side programming. The flash EEPROM array, when programmed from the source side exhibits fast programming rates. Additionally, source side programming of arrays having different physical characteristics (e.g. transistor cell channel length) exhibit tighter program rate distributions than for the same arrays in which drain side programming is used.

Abstract: A circuit is provided which contains memory, logic, arithmetic and control circuitry needed to generate all or part of a frame for use in video processing and animation as well as digital signal and image processing. One or more such circuits are provided on an integrated circuit. A video or image frame generation system is constructed from one or more of these integrated circuits, optionally with additional memory circuitry, to provide exceptional performance in frame production for animation, particularly 3-D and other high performance applications such as medical imaging, virtual reality and real-time scene generation in video games and simulation environments. The circuit(s) are used to process high speed object-oriented graphics related streams such as proposed by MPEG 4, as well as act as a single chip JAVA engine with highly optimized numeric performance.

Abstract: An arithmetic circuit for calculating floating point operations. The circuit comprises first and second blocks of consecutive logic cells. Each logic block has a first cell and a last cell, with the first cell through the next to last cell having an output that is coupled to the next adjacent cell. The coupling of the last cells of the first and second logic blocks depends on the value of a control signal. A comparator may be used to generate the control signal.

Abstract: An expansion board architecture and method for configuring the board. The board comprises a controller chip, a parallel bus, a memory for storing a plurality of configuration data bits, and a control line. The controller chip controls the operation of the board and has an internal register for storing a plurality of data bits. The parallel bus transfers data bits between the controller chip and other components on the board and is connected to the memory. The control line is connected between the controller and the memory for enabling the output of the memory to transfer the configuration bits to the register over the bus.

Abstract: A flash memory device includes a substrate having first and second wells. The first well is defined within the second well. A plurality of trenches defines the substrate into a plurality of sub-columnar active regions. The trenches is formed within the first well and extends into the second well. A plurality of flash memory cells are formed on each of the sub-columnar active regions.

Abstract: The invention concerns integrated circuits in which a MACRO is embedded in a standard cell array. One level of metal is devoted exclusively to non-local interconnect, and a layer of polysilicon is devoted to local interconnect, thereby saving significant space.

Abstract: The invention concerns integrated circuits in which a MACRO is embedded in a standard cell array. One level of metal is devoted exclusively to non-local interconnect, and a layer of polysilicon is devoted to local interconnect, thereby saving significant space.

Abstract: A variable rate correlation circuit for conserving power includes a variable clock source, a local PN source, and a correlator. The local PN source further includes a local generator and a resampler. The variable clock source provides a normal clock rate and a lower clock rate. The local generator supplies the local PN sequence at the normal clock rate. The resampler receives the local PN sequence sampled at the normal clock rate and outputs the local PN sequence sampled at the lower clock rate. The correlator receives the lower sampled local PN sequence, the received PN sequence, and the lower clock rate signal, correlating the received and local PN sequences at the lower clock rate to produce a. correlated result.

Abstract: An architecture for distributing digital information to subscriber units wherein selection from among multiple digital services is accomplished by transmitting a tuning command from a subscriber unit to an intermediate interface. The intermediate interface selects the desired service from a broadband network and transmits it to the subscriber unit over a bandwidth-constrained access line. The bandwidth-constrained access line may be implemented with existing infrastructure, yet the subscriber unit may access a wide variety of digital information -available on the broadband network. Universal broadband access is thus provided at low cost.

Abstract: An improved method of manufacturing active matrix displays with ESD protection through final assembly and in process testing and repair capabilities. At least a first set of shorting bars is formed adjacent the row and column matrix. The shorting bars are respectively coupled to one another in series to allow testing of the matrix elements. A first shorting bar is coupled to the row lines and a second shorting bar is coupled to the column lines. The shorting bars can remain coupled to the matrix through final assembly to provide ESD protection and final assembly and testing capability.

Abstract: The invention concerns integrated circuits in which a MACRO is embedded in a standard cell array. One level of metal is devoted exclusively to non-local interconnect, and a layer of polysilicon is devoted to local interconnect, thereby saving significant space.

Abstract: The invention concerns a BI-CMOS process, in which Field-Effect Transistors (FETs) and Bipolar Junction Transistors (BJTs) are manufactured on a common substrate. In several processing steps, FET structures are formed simultaneously with BJT structures. For example, in one step, polysilicon gate electrodes for the FETs and polysilicon emitters for the BJTs are formed simultaneously. In another aspect of the invention, a polysilicon layer is used to reduce channeling which would otherwise occur during an implant step.

Abstract: The invention concerns the use of spin-on-glass (SOG) to bond two layers of semiconductor together, in order to form a Silicon-on-Insulator (SOI) structure. One type of SOG is a cross-linked siloxane polymer, preferably of the poly-organo-siloxane type, comprising a carbon content of at least 5 atomic weight percent.

Abstract: The invention concerns a stylus for use with a digitizing tablet. The stylus stores information which identifies characteristics of a user's handwriting. These characteristics are transmitted to a computer when the user interfaces with the computer, and are used by the computer to recognize the user's handwriting.

Abstract: A method of erasing electrically a programmable memory cell which cell includes a transistor formed in a region of semiconductor material. The transistor has a source region, a drain region, a floating gate, and a control gate. The method comprises lowering the control gate to a potential of about −9 volts, disconnecting the source and drain regions from any potential source, and placing the region of semiconductor material at a potential of about 9 volts.

Abstract: A low dielectric material is applied, as by spinning on, over the passivation layer of a semiconductor chip to fill the gaps which may exist between the top layer metal lines, and thereby minimize the possibility of cross talk which might otherwise be present between those lines.

Abstract: A low dielectric material is applied, as by spinning on, over the passivation layer of a semiconductor chip to fill the gaps which may exist between the top layer metal lines, and thereby minimize the possibility of cross talk which might otherwise be present between those lines.

Abstract: An image sensor having an integrated address controller for use in an electronic camera. Providing both functions on a single integrated circuit reduces the number of external pins and external circuitry required to process an image. The integrated address controller also provides several addressing modes allowing for programmable format data transfer from the image sensor. This integrated controller not only allows addressing the sensor array in a raster scan, but it also allows other addressing modes including block addressing (useful for block based compression methods like JPEG, MPEG or H.261) and region addressing (by which one could implement pan and tilt functions). Thus, this sensor and address controller combination provides data in the format required for higher level functions, as opposed to forcing the user to convert raster scan to an appropriate format using complicated external circuitry.

Abstract: A low dielectric material is applied, as by spinning on, over the passivation layer of a semiconductor chip to fill the gaps which may exist between the top layer metal lines, and thereby minimize the possibility of cross talk which might otherwise be present between those lines.

Abstract: A low dielectric material is applied, as by spinning on, over the passivation layer of a semiconductor chip to fill the gaps which may exist between the top layer metal lines, and thereby minimize the possibility of cross talk which might otherwise be present between those lines.