Abstract: A method of chip interleaving in direct sequence spread spectrum communications. A binary code sequence is chosen to have a length N=2.sup.k -1 and to be self-orthogonal. A data string of M=QN.+-.1 bits, where Q is a positive integer, is multiplied sequentially with the binary code sequence until N chip frames of M chips each are produced. These chip frames are transmitted to a receiver, and recovered in an equally straightforward manner. The integers Q and N are chosen according to transmission conditions.

Abstract: A static pass-transistor logic gate design which incorporates the new technique of forecasted-restoration of the output logic-level. The forecasting of the need for output logic-level restoration is accomplished by the connection of restoration circuit inputs to a logic-gate input, which provides the appropriate logic input signal to the restoration circuit, to properly control the state of the restoration circuit. Logic gate inputs which are unnecessary in the determine of the appropriate restoration circuit input logic state are connected to the appropriate input logic levels. Further, there is potential for significant area savings, with accompanying economic benefit when using the FRCPG logic, due to the reduced transistor count of FRCPG.