Patents Assigned to I-Cube, Inc.
  • Patent number: 6356111
    Abstract: A high-speed N×M crosspoint switch selectively routes input signals arriving at any of N input terminals to one or more of M output terminals through a switch cell array having N rows and M columns of switch cells, each for selectively providing a signal path between one input terminal and one output terminal. Each switch cell contains a first memory cell holding a data bit, a second memory cell holding a control bit, and a transistor for making or braking a signal path in response to the control bit. This switch cell architecture enables the crosspoint switch to operate in normal, implied disconnect and broadcast modes. In the normal mode a controller creates a routing pattern by writing data bits to the second memory cells and then signals all switch cells to transfer their data bits into the first memory cells. In the implied disconnect mode, when any cell of a column is signaled to make a path, all other cells along that column automatically break their paths.
    Type: Grant
    Filed: December 12, 2000
    Date of Patent: March 12, 2002
    Assignee: I-Cube, Inc.
    Inventor: William E. Moss
  • Patent number: 6249528
    Abstract: A network routing switch includes a crosspoint switch, a set of Ethernet I/O ports, a set of ATM I/O ports, a reassembly unit for converting ATM transmissions into Ethernet transmissions, and a segmentation unit for converting Ethernet transmissions into ATM transmissions. As an ATM I/O port receives cells of an ATM transmission from an external source it stores them until the transmission is complete and then sends the ATM transmission through the crosspoint switch either to a forwarding ATM port or to the reassembly unit depending on whether the ATM transmission is to be forwarded as an ATM or Ethernet transmission. When the reassembly unit receives an ATM transmission it converts it to an Ethernet transmission and forwards it through the crosspoint switch to a forwarding Ethernet I/O port.
    Type: Grant
    Filed: March 12, 1998
    Date of Patent: June 19, 2001
    Assignee: I-Cube, Inc.
    Inventor: Piyush Kothary
  • Patent number: 6212194
    Abstract: A local area network routing switch for routing data transmissions between buses includes a set of input buffers, each for receiving and storing successive data transmissions arriving via a corresponding one of the bus. The switch also includes a set of output buffers for forwarding data transmissions outward via a corresponding bus, and a routing system for selectively routing data transmissions from the input buffers to the output buffers in response to routing requests from the input buffers. The routing system sends STATUS data to each input buffer indicating which output buffers are busy receiving data transmissions and which output buffers are idle. An input buffer makes a routing request only when it stores a data transmission to be forwarded to an idle output port. If its longest-stored data transmission is destined for a busy output port, it may send a routing request for a more recently stored data transmission if that data transmission is to be forwarded to an idle output buffer.
    Type: Grant
    Filed: August 5, 1998
    Date of Patent: April 3, 2001
    Assignee: I-Cube, Inc.
    Inventor: Wen-Jai Hsieh
  • Patent number: 6208644
    Abstract: A network switch routes data transmissions between network stations, each data transmission including network addresses of the source and destination network stations. The network switch includes a set of input/output (I/O) ports each for receiving data transmissions from and transmitting data transmissions to a subset of the network stations. Each I/O port is identified by a “physical” port ID and a “logical” port ID. While each I/O port's physical port ID is unique, all I/O ports that can route data to the same subset of network stations share the same logical port ID. Each I/O port receiving a data transmission from a network station sends its logical port ID and the network addresses included in the data transmission to an address translation system.
    Type: Grant
    Filed: March 12, 1998
    Date of Patent: March 27, 2001
    Assignee: I-Cube, Inc.
    Inventors: Donald Robert Pannell, Robert Donald Hemming
  • Patent number: 6151644
    Abstract: A dynamically configurable network buffer includes a buffer manager organizing a buffer memory into a set of uniform sized packet buffers, each of which is large enough to store the largest possible data packet that may be transmitted through the network switch. The buffer manager further subdivides each packet buffer into a set of smaller packet cells of uniform size. When an incoming data packet arrives at the network buffer, the buffer manager determines its size. If the packet is too large to be stored in a single packet cell, the buffer manager stores the packet by itself in an unoccupied packet buffer. If the packet is small enough to be stored in a single packet cell, the buffer manager stores the packet in an unoccupied packet cell. The network buffer can increase or decrease packet cell size in response to input configuration data.
    Type: Grant
    Filed: April 17, 1998
    Date of Patent: November 21, 2000
    Assignee: I-Cube, Inc.
    Inventor: Chun-Chu Archie Wu
  • Patent number: 5940596
    Abstract: A network switch forwards data packets between network stations connected to its input and output ports. Each data packet includes the network address of a destination station. The receiving input port consults an address translation system including a local address translation cache within each input port for caching recently used address-to-port translation information, a set of secondary address translation units each serving a separate cluster of input ports for caching a larger amount of recently used address translation information, and a main address translation unit storing address-to-port translation information for all network stations. An input port not having appropriate translation information in its local cache sends an address translation request to a secondary address translation unit. A secondary address translation unit not having appropriate address translation information to respond to the request, forwards the request to the main address translation unit.
    Type: Grant
    Filed: August 4, 1997
    Date of Patent: August 17, 1999
    Assignee: I-Cube, Inc.
    Inventors: Sundar Rajan, Kent Blair Dahlgren
  • Patent number: 5884101
    Abstract: A buffer monitor includes a first counter for counting bits of incoming data as they arrive at a data buffer that stores and then forwards the incoming data. Each bit of outgoing data resets the first counter's count. If its count reaches a first limit before being reset by an outgoing data bit, the first counter asserts an alarm. The buffer monitor also includes a second counter for counting bits of outgoing data as they depart the buffer. Each bit of incoming data resets the second counter's count. If its count reaches a second limit level before being reset by an incoming data bit, the second counter asserts an alarm. The first counter will sound an alarm when the buffer fails to forward output data after having received a substantial amount of input data. The second counter will assert an alarm when the buffer has forwarded a substantial amount of output data without having received any input data.
    Type: Grant
    Filed: April 17, 1998
    Date of Patent: March 16, 1999
    Assignee: I-Cube, Inc.
    Inventor: Chun-Chu Archie Wu
  • Patent number: 5790048
    Abstract: A crosspoint switch routes signals between its terminals in routing patterns defined by routing data from a host controller. The crosspoint switch includes an array of pass transistors. Each pass transistor, when turned on, provides a signal path interconnecting a separate, unique pair of the switch terminals. The crosspoint switch also includes two static random access memory banks. Each memory bank stores routing data defining a separate routing pattern and produces a separate set of output signals reflecting its stored data. A multiplexer delivers the output signals of a selected one of the memory banks to the switch array for controlling its pass transistors so that the switch array implements the routing pattern defined by the data in the selected memory bank. By loading routing data defining different routing patterns into the two memory banks, a host controller can thereafter quickly make the crosspoint switch alternate between the two routing patterns by toggling the multiplexer's control input.
    Type: Grant
    Filed: October 30, 1997
    Date of Patent: August 4, 1998
    Assignee: I-Cube, Inc.
    Inventors: Wen-Jai Hsieh, Chi-Song Horng, Chun Chiu Daniel Wong, Gerchih Chou, Shrikant Sathe, Kent Dahlgren
  • Patent number: 5784003
    Abstract: A local area network switch includes input and output ports for receiving and transmitting broadcast and unicast data transmissions from and to corresponding network stations and a crosspoint switch for selectively routing data transmissions between the ports. All input ports have one connection to the crosspoint switch for forwarding incoming broadcast and unicast data transmissions to the crosspoint switch. Each output port has a unique unicast link to the crosspoint switch for receiving unicast transmissions directed solely to its corresponding network station. All output ports also share a second broadcast link to the crosspoint switch for receiving broadcast transmissions directed to all network stations. The crosspoint switch routes each unicast transmission from an input port only to the appropriate output port via the output port's unicast link and routes broadcast transmission from an input port to all output ports via the common broadcast link.
    Type: Grant
    Filed: March 25, 1996
    Date of Patent: July 21, 1998
    Assignee: I-Cube, Inc.
    Inventor: Kent Blair Dahlgren
  • Patent number: 5781717
    Abstract: An MxN dynamic spare column replacement memory system for storing M N-bit data words includes a random access memory (RAM) formed by a rectangular array of M rows and N+S columns of single-bit memory cells. Each row has a unique address and stores an N-bit word using a selected set of N of its N+S cells. An N-line parallel data bus provides data access to the DRAM. Responding to a switching instruction from a switch controller at the start of each memory access cycle, a crossbar switch selectively connects each of the N lines of the data bus to a separate one of the N+S columns. Thus during a memory read or write access cycle the N data lines access N cells of an addressed row columns. The remaining S cells of the row are unused. A host computer occasionally checks the DRAM for defective memory cells, and upon finding a defective cell or cells in any row, the host stores the row address and a switching instruction in the switch controller.
    Type: Grant
    Filed: September 19, 1996
    Date of Patent: July 14, 1998
    Assignee: I-Cube, Inc.
    Inventors: Chun-Chu Archie Wu, Chun Chiu Daniel Wong
  • Patent number: 5754791
    Abstract: A network switch routes data transmissions between uniquely addressed network stations connected to input and output ports of the switch. The switch includes a hierarchical address translation system for relating network addresses of stations to receive incoming transmission to the switch ports to which they are connected. The translation system includes a central translation unit having a memory for storing a mapping entry for each network station, the entry mapping the station's network address to its switch port. The system also includes a local translation unit in each input port. Each local translation unit contains a local cache memory for storing a smaller subset of the mapping entries stored by the central translation unit. When a data transmission arrives at an input port directed to a network address, the input port looks for an entry in its cache memory mapping that network address to an output port.
    Type: Grant
    Filed: March 25, 1996
    Date of Patent: May 19, 1998
    Assignee: I-Cube, Inc.
    Inventors: Kent Blair Dahlgren, Daniel J. Bedell
  • Patent number: 5734334
    Abstract: An electronic crossbar switch employs a switch array for selectively routing digital and analog signals between its terminals. A separate port for each terminal provides a path for digital and analog signals flowing in and out of the switch. Each port can be configured to operate with or without tristate buffering under control of a tristate control signal, to optionally latch input or output signals in response to clock and clock enable signals, and to buffer signals passing in or out of the switch terminal with or without an input direction control signal. A set of control inputs are provided in common to all ports, allowing an external host to transmit control signals in parallel to each port. Each port may be programmed to select any of its control inputs as its tristate, clock enable, clocking or direction control signal.
    Type: Grant
    Filed: August 17, 1995
    Date of Patent: March 31, 1998
    Assignee: I-Cube, Inc.
    Inventors: Wen-Jai Hsieh, Chi-Song Horng, Chun Chiu Daniel Wong, Gerchih Chou, Shrikant Sathe, Kent Dahlgren
  • Patent number: 5717871
    Abstract: An electronic crossbar switch employs a switch array for selectively routing signals between its terminals. A separate port provided for each terminal buffers signals flowing in and out of the switch. Each port can be configured to operate with or without tristate buffering under control of a tristate control signal, to optionally latch input or output signals in response to clock and clock enable signals, and to buffer signals passing in or out of the switch terminal in response to a direction control signal. A set of control inputs are provided in common to all ports, allowing an external host to transmit control signals in parallel to each port. Each port may be programmed to select any of its control inputs as its tristate, clock enable, clocking or direction control signal. A parallel "key" bus is also provided in common to all ports for conveying a key address from the host controller.
    Type: Grant
    Filed: August 17, 1995
    Date of Patent: February 10, 1998
    Assignee: I-Cube, Inc.
    Inventors: Wen-Jai Hsieh, Chi-Song Horng, Chun Chiu Daniel Wong, Gerchih Chou, Shrikant Sathe, Kent Dahlgren
  • Patent number: 5710550
    Abstract: A field programmable interconnect device (FPID) selectively routes signals between signal ports in response to commands from a host controller. Each command includes an address and data. The FPID includes an array of switch cells, each interconnecting a separate pair of the ports and each having first and second control signal inputs. When the first and second control signals are both asserted, the switch cell provides a signal path between the pair of the ports it interconnects. The FPID includes first and second sets of memory cells for storing data. Each first memory cell corresponds to a separate one of the switch cells and selectively asserts or deasserts the first control signal input to the corresponding switch cell according to its stored data. Each second memory cell corresponds to a separate group of switch cells and selectively asserts or deasserts the second control signal input to each switch cell of the corresponding group according to its stored data.
    Type: Grant
    Filed: August 17, 1995
    Date of Patent: January 20, 1998
    Assignee: I-Cube, Inc.
    Inventors: Wen-Jai Hsieh, Chi-Song Horng, Chun Chiu Daniel Wong, Gerchih Chou, Shrikant Sathe
  • Patent number: 5689644
    Abstract: A local area network switch includes a set of input ports each receiving and storing incoming packets from a corresponding network station, a set of output ports each forwarding packets to a corresponding network station, and a switching system for routing packets from the input ports to the output ports. The output ports are interconnected to form an output token passing ring and the input ports are interconnected to form an input token passing ring. Whenever an idle output port receives the output token, it holds the output token and signals the input ports to start an input token passing cycle. During an input token passing cycle, an input port storing a packet destined for an output token holder terminates the input token passing cycle when it receives the input token and signals the switching system to establish a connection to the output token holder. To fairly distribute arbitration priority, input and output ports starting positions are rotated for successive input and output token passing cycles.
    Type: Grant
    Filed: March 25, 1996
    Date of Patent: November 18, 1997
    Assignee: I-Cube, Inc.
    Inventors: Ger-Chih Chou, Kent Blair Dahlgren, Wen-Jai Hsieh
  • Patent number: 5625780
    Abstract: A programmable backplane includes a motherboard having slots for receiving printed circuit boards (PCBs). A field programmable interconnect device (FPID) mounted on the motherboard includes a programmable crosspoint switch for selectively routing signals between terminals of the PCBs. The routing is determined by input programming data. The FPID bi-directionally buffers all signals passing between ports of the crosspoint switch and the PCB terminals and can alter signal routing dynamically in response to routing instructions generated by instruction sources mounted on or connected to the PCBs. The programmable backplane may be used as a communication hub in a communication network or parallel processing system.
    Type: Grant
    Filed: November 2, 1994
    Date of Patent: April 29, 1997
    Assignee: I-Cube, Inc.
    Inventors: Wen-Jai Hsieh, Chi-Song Horng, Chun C. D. Wong
  • Patent number: 5559971
    Abstract: A hierarchical crosspoint array is formed by switch cells occupying separate rectangles in a common plane of an integrated circuit. The switch cells are arranged to form square subarrays which, along with a corresponding set of control cells form a compact square shaped crosspoint array. Each switch cell includes three I/O lines crossing in two orthogonal directions and mating with I/O lines of adjacent switch cells to form two orthogonal arrays of I/O lines. Pairs of orthogonal I/O lines are permanently interconnected where they intersect in switch cells along a main diagonal of the array to provide signal paths leading from separate ports along the edges of the array each extending the length and width of the crosspoint array. Each switch cell of a subarray selectively interconnects two such signal paths to provide a signal path between two ports in response to a combination of states of a bit stored in the switch cell and a bit stored in a control cell corresponding to the subarray.
    Type: Grant
    Filed: November 2, 1991
    Date of Patent: September 24, 1996
    Assignee: I-Cube, Inc.
    Inventors: Wen-Jai Hsieh, Chi-Song Horng, Chun C. D. Wong
  • Patent number: 5530814
    Abstract: A hierarchical crossbar switch includes several switch arrays, each switch array including several switch cells. Each switch cell interconnects a unique pair of signal ports and provides a bi-directional signal path between the signal ports it interconnects when switched on by an enabling signal. A first memory array stores input data indicating particular switch cells to be switched on. A second memory array stores input data indicating particular ones of the switch arrays to be enabled. The crossbar switch also includes a logic cell array that reads the data stored in the first and second memories and sends separate control signals to each switch cell. Each control signal switches on the switch cell to which it is sent when data in the first and second memory arrays indicate both that the switch cell is to be switched on and that the switch cell array including the switch cell is to be enabled.
    Type: Grant
    Filed: November 2, 1994
    Date of Patent: June 25, 1996
    Assignee: I-Cube, Inc.
    Inventors: Chun C. D. Wong, Wen-Jai Hsieh, Chi-Song Horng
  • Patent number: 5465056
    Abstract: A field programmable interconnect device (FPID) includes a set of ports and an array of switch cells for selectively interconnecting pairs of the ports. The switch cells are organized into a hierarchy of subarrays, and a control cell is provided for each subarray. Each switch cell includes a crosspoint switch and a single-bit memory. A bit stored in the memory indicates whether the switch, when enabled, is to interconnect its pair of FPID I/O ports. A data bit stored in each control cell indicates whether all switching cells of an associated subarray are enabled. In a "rapid connect" mode of operation, the FPID sets the state of the bit stored in any individual switch or control cell in response to parallel input data identifying the cell and indicating the state of the bit to be stored in the cell. In the rapid connect mode, the FPID can be programmed to rapidly switch connections between individual lines or between parallel buses connected to its ports.
    Type: Grant
    Filed: November 2, 1994
    Date of Patent: November 7, 1995
    Assignee: I-Cube, Inc.
    Inventors: Wen-Jai Hsieh, Chi-Song Horng, Chun C. D. Wong
  • Patent number: 5428800
    Abstract: A bi-directional buffer includes first and second unidirectional buffers connected for retransmitting signals in opposite directions between first and second buses. When an external bus driver pulls the first bus low, the first unidirectional buffer pulls the second bus low and generates a signal inhibiting the second unidirectional buffer from actively driving the first bus. When the external bus driver allows the first bus to return to the high logic level, the first unidirectional buffer temporarily supplies a high charging current to the second bus to quickly pull it up. Similarly, when an external bus driver pulls the second bus low, the second unidirectional buffer pulls the first bus low and generates a signal inhibiting the first unidirectional buffer from actively driving the second bus. When the external bus driver allows the second bus to return to the high logic level, the second buffer temporarily supplies a high charging current to the first bus to quickly pull it up.
    Type: Grant
    Filed: October 13, 1992
    Date of Patent: June 27, 1995
    Assignee: I-Cube, Inc.
    Inventors: Wen-Jai Hsieh, Yih-Chyun Jenq, Chi-Song Horng, Keith Lofstrom