Patents Assigned to I.P. Holdings
  • Patent number: 7211742
    Abstract: A fire resistant, forced air cooled enclosure for one or more computer digital data storage devices is provided. An operable digital data storage device is mounted in a fire resistant enclosure. One or more openings are formed in the enclosure. A movable fire resistant hatch is positioned adjacent each of the openings and each hatch is movable between a closed position in which it closes the opening and an open position allowing ambient air to pass therethrough. A fan is positioned either inside or outside of the enclosure for actively driving ambient air through the opening to cool the data storage device. A hatch closure system is provided for closing each of said hatches automatically in the presence of a threshold temperature. The hatch closure system includes a temperature sensitive element which, when activated in the presence of the threshold temperature, causes the hatch to move to its closed position.
    Type: Grant
    Filed: April 22, 2005
    Date of Patent: May 1, 2007
    Assignee: Auburn I.P. Holdings, LLC
    Inventors: Robby Jay Moore, Jeffrey Bart Abramson, John Arthur Hendricks
  • Patent number: 7122216
    Abstract: This invention relates to methods for treating oil bearing vegetable material, especially oilseeds. Methods of the invention provide for the isolation of certain components of oil bearing vegetable material, including isoflavones, vegetable oil, and a phosphatide fraction substantially free of flatulence-promoting undigestable oligosaccharides and substantially lacking objectionable taste. Methods of the invention also provide for the production of various protein-containing fractions substantially free of flatulence-promoting undigestable oligosaccharides and substantially lacking objectionable taste.
    Type: Grant
    Filed: June 16, 2003
    Date of Patent: October 17, 2006
    Assignee: I.P. holdings, L.L.C.
    Inventors: Dick Copeland, George L. Hoover, W. Maurice Belcher
  • Patent number: 6490725
    Abstract: A video jukebox service has a world-wide array of file servers interconnected by data links and having video input apparatus. Each file server has a plurality of connected clients. Video clippings input at the video input apparatus are shared with the other file servers and stored in a database at each file server. Clients are notified of availability of video clippings, and clippings are downloaded to client stations on demand. In a preferred embodiment, the file server network is a toriodal arrangement, and client communication nodes equal in number to the number of file servers are interconnected in a toroidal fashion as well. Individual client stations are connected to individual ones of the client communication nodes, with the overall network in the form of nested toroids.
    Type: Grant
    Filed: December 19, 2000
    Date of Patent: December 3, 2002
    Assignee: Elonex I.P. Holdings, Ltd.
    Inventor: Dan Kikinis
  • Patent number: 6426423
    Abstract: This invention relates to improved methods for treating phosphatide-containing mixtures. More particularly, this invention relates to methods for recovering purified vegetable oil, aqueous organic acid, and organic acid-treated phosphatide from a phosphatide-containing mixture comprising an acid-and-oil mixture obtained from organic acid refining of vegetable oil.
    Type: Grant
    Filed: February 2, 2001
    Date of Patent: July 30, 2002
    Assignee: I.P. Holdings
    Inventors: Dick Copeland, W. Maurice Belcher
  • Patent number: 6423857
    Abstract: This invention relates to improved methods for recovering fatty acids during purification of vegetable oil. More particularly, this invention relates to improved methods for recovering fatty acids from a phosphatide-containing material obtained from organic acid refining of vegetable oil.
    Type: Grant
    Filed: March 14, 2001
    Date of Patent: July 23, 2002
    Assignee: I.P. Holdings
    Inventors: Dick Copeland, W. Maurice Belcher
  • Patent number: 5964848
    Abstract: An IDE interface communicates with peripheral devices not conforming to ST506 specification by providing firmware to microcontrollers mounted on the non-conforming peripheral devices to translate between the data structure of an ST506 specification device and the data structure of the non-conforming device. CD-ROM and cartridge tape drive communication is provided. An enhanced IDE interface communicates with multiple peripheral devices by adding a selective ability to the firmware of the conventional IDE interface.
    Type: Grant
    Filed: June 4, 1998
    Date of Patent: October 12, 1999
    Assignee: Elonex I.P. Holdings, Ltd.
    Inventors: Dan Kikinis, Pascal Dornier
  • Patent number: 5954807
    Abstract: An apparatus and methods are provided for pre-compressing data to be sent to a peripheral device in a computer system, sending the data to the peripheral device as a compressed data stream, and decompressing the data for use in the peripheral device in a real-time format. In a preferred embodiment, a unique peripheral device controller is provided having a data handling and decompression pipeline for receiving and decompressing an incoming compressed data stream in concert with a state machine for sensing the states of elements of the peripheral device, and for providing the decompressed data stream to data-using elements of the peripheral device. The peripheral device can be any device for which large amounts of data are typically needed, including, but not limited to printers, video displays, robotic driving devices, and data recording and media writing devices. Alternative methods are disclosed for compressing and decompressing data in systems according to the invention.
    Type: Grant
    Filed: December 4, 1996
    Date of Patent: September 21, 1999
    Assignee: Elonex I.P. Holdings, Ltd.
    Inventor: Dan Kikinis
  • Patent number: 5920727
    Abstract: A system for managing power levels for a general purpose computer having a standby and a full-power mode of operation provides apparatus and a method for monitoring times of user input and control routines for using the times of user input to calculate optimum times for initiating full power operation and standby mode. The control routines are configured to provide the optimum times to a real time clock that remains powered in the standby mode, which triggers switching elements to initiate full power and standby mode. In one embodiment of the system, startup and standby may be initiated either by user input or automatically by the power management system. Startup and standby initiation times may be different for different days and time periods based on both preprogrammed and calculated values.
    Type: Grant
    Filed: August 7, 1997
    Date of Patent: July 6, 1999
    Assignee: Elonex I.P. Holdings Ltd.
    Inventors: Dan Kikinis, Pascal Dornier
  • Patent number: 5919263
    Abstract: A system for reducing power consumption of a computer peripheral device connected to a host computer during periods of inactivity of the host computer has a dedicated input for initiating power management operations. When the dedicated input is sensed a timer is started and a power management command is sent to the peripheral device, initiating a reduced-power mode other than off. In a preferred embodiment the system also starts a timer when the dedicated input is sensed, and after a predetermined time a second power management command is sent triggering a second reduced-power mode for the peripheral. The system is adapted to peripheral devices such as video displays and printers.
    Type: Grant
    Filed: April 23, 1998
    Date of Patent: July 6, 1999
    Assignee: Elougx I.P. Holdings L.T.D.
    Inventors: Dan Kikinis, Pascal Dornier
  • Patent number: 5919262
    Abstract: An integrated CPU has an on-board switching voltage regulator with an electrically-erasable programmable read-only memory electronically accessible for storing a feedback reference coefficient for control. In further embodiments, output voltage is tuned via a second EEPROM storing an electronically accessible value in concert with a solid-state resistor ladder. In other embodiments, signals on interrupt lines to the CPU are monitored to provide a prewarning of impending activity by the CPU requiring dramatically increased current flow. In yet other embodiments, solid state circuitry is provided to reduce or eliminate capacitors used for dealing with input current surges to the CPU.
    Type: Grant
    Filed: February 2, 1998
    Date of Patent: July 6, 1999
    Assignee: Elonex I.P. Holdings, Ltd.
    Inventors: Dan Kikinis, Pascal Dornier
  • Patent number: 5880719
    Abstract: A system for managing power states for a video display monitor for a computer during periods of operator inactivity senses the presence or absence of signals provided to the video display monitor for forming an image on the monitor, such as red (R), green (G), blue (B) and horizontal synchronization (HSYNC) and vertical synchronization (VSYNC) signals. Time sensing apparatus at the host senses input activity, and in one embodiment suspends a signal provided to the monitor. Sensing and control circuits in the monitor sense the absence of the signal normally supplied to the monitor, and control power-using circuitry in the monitor in response. In an embodiment applicable to monitors having a microprocessor, the system may be incorporated entirely in software at the host and the monitor. In dumb monitors the system requires add-in or add-on devices cooperating with software.
    Type: Grant
    Filed: July 11, 1997
    Date of Patent: March 9, 1999
    Assignee: Eloney I.P. Holdings L.T.D.
    Inventor: Dan Kikinis
  • Patent number: 5870624
    Abstract: A personal I/O device incorporates a scanner and a printer apparatus in a common assembly with a document drive designed to feed a single document or blank sheet past both the scanner and the printer apparatus. The I/O device comprises control circuitry for driving and coordinating the document drive with the scanner and the printer apparatus, and communication apparatus for communicating with a remote computer host. In one embodiment the device comprises a platen with retaining mechanisms for holding a document in place while the platen is moved by the scanner and the printer apparatus. The device in some embodiments is integrated with a computer in a common enclosure, in others with a monitor stand, and in others provides a stand-alone configuration. The device provides a small, relatively inexpensive, and compact package which may be placed at a user's computer workstation.
    Type: Grant
    Filed: September 17, 1997
    Date of Patent: February 9, 1999
    Assignee: Elonex I.P. Holdings, Ltd.
    Inventor: Dan Kikinis
  • Patent number: 5861873
    Abstract: A modular computer has a framework with module bays for receiving CPU modules, power modules, and peripheral function modules such as floppy and hard disk drives. The framework has a built-in compressed bus and a variety of function modules which can be plugged into any one of the module bays. Function modules include, but are not limited to, CPU, power, floppy disk, hard disk, RAM memory, LAN communication, modem, FAX communication, and data acquisition. In some embodiments function modules are provided for communicating with separate input means, such as voice, keyboards, and pen-pads. In one aspect the module bays and the function modules are configured according to dimensional and connective standards of the Personal Computer Memory Card International Association. There are additionally pointer devices configured to be stored in compartments in the modular computer.
    Type: Grant
    Filed: November 7, 1994
    Date of Patent: January 19, 1999
    Assignee: Elonex I.P. Holdings, Ltd.
    Inventor: Dan Kikinis
  • Patent number: 5835955
    Abstract: A disk array server has a cache and a log drive wherein data blocks, as received are written synchronously to both the cache and the log drive, the cache being written back to the disk array as opportunity affords. The log drive is managed so, when full, data is overwritten in the order first stored on the log drive. Data blocks written to the log drive are flagged as to whether the same block in cache has been written to the disk array, and the flags are updated as the cache is written back to the disk array. In the event of a power failure, data lost from the volatile cache as not yet written to the disk array may be recovered from the log drive. In one embodiment, the recovery is automatic on startup after a power failure.
    Type: Grant
    Filed: August 25, 1997
    Date of Patent: November 10, 1998
    Assignee: Elonex I. P. Holdings
    Inventors: Pascal Dornier, Dan Kikinis
  • Patent number: 5832214
    Abstract: A secure password log-in system for a computer having a keyboard with a keyboard data link to a keyboard controller comprises a data diverter circuit interposed in the keyboard data link between the keyboard and the keyboard controller; a boot read-only memory (ROM) having at least one pre-stored password for comparison with a password entered by a user; a boot controller connected to the boot ROM; and a bypass data link between the data diverter circuit and the boot controller. The boot controller, executing a boot routine from the boot ROM, causes entered keystrokes constituting a password to be diverted via the bypass data link to the boot controller.
    Type: Grant
    Filed: April 29, 1997
    Date of Patent: November 3, 1998
    Assignee: Elonex I.P, Holdings, Ltd.
    Inventor: Dan Kikinis
  • Patent number: 5821924
    Abstract: A system for lowering the power output of a computer peripheral device connected to a host computer during periods of inactivity of the host or the peripheral device senses a power management command at the peripheral device generated at the host computer. Time sensing means at the host senses inactivity, and gerating circuitry generates a power-management command. Detection circuitry in the peripheral device senses the power-management command, and controls power-using circuitry in the peripheral device in response. In an embodiment applicable to peripherals having a microprocessor, the system may be incorporated entirely in software at the host and the peripheral device. In dumb devices, the system requires add-in and/or add-on apparatus cooperating with software.
    Type: Grant
    Filed: October 26, 1995
    Date of Patent: October 13, 1998
    Assignee: Elonex I.P. Holdings, Ltd.
    Inventors: Dan Kikinis, Pascal Dornier
  • Patent number: 5812870
    Abstract: A digital assistant computer device has an audio input interface and a memory adapted to receive audio input of significant time extent, and to convert the input and store it as a digital sound file. The digital assistant in one embodiment has a CPU and bus, input and display apparatus, on-board memory, and a microphone and digital signal processor for accepting and converting audio input.
    Type: Grant
    Filed: November 22, 1996
    Date of Patent: September 22, 1998
    Assignee: Eloner I.P. Holdings Ltd.
    Inventors: Dan Kikinis, Pascal Dornier, William J. Seiller
  • Patent number: 5805921
    Abstract: An IDE interface communicates with peripheral devices not conforming to ST506 specification by providing firmware to microcontrollers mounted on the non-conforming peripheral devices to translate between the data structure of an ST506 specification device and the data structure of the non-conforming device. CD-ROM and cartridge tape drive communication is provided. An enhanced IDE interface communicates with multiple peripheral devices by adding a selective ability to the firmware of the conventional IDE interface.
    Type: Grant
    Filed: July 11, 1995
    Date of Patent: September 8, 1998
    Assignee: Elonex I. P. Holdings Ltd.
    Inventors: Dan Kikinis, Pascal Dornier
  • Patent number: 5805902
    Abstract: An interrupt control circuit for use in a computer system has a CPU, a peripheral I/O device, and a bus having address lines for carrying signals to and from the peripheral I/O device. Interrupt requests generated by the I/O device are encoded as address signals which are transmitted on the address bus lines. A predetermined set of addresses are set aside to represent the interrupt requests. The interrupt control circuit is coupled to the address bus lines to receive the encoded interrupt requests. The interrupt control circuit has an address decoder which receives address signals from the I/O device. When these address signals represent an address within the predetermined set of addresses set aside to represent the interrupt requests, the address decoder uses the address signals to create a plurality of interrupt control signals. The interrupt control signals are provided to an interrupt latch/decoder which uses the interrupt control signals to create interrupt request signals.
    Type: Grant
    Filed: October 28, 1997
    Date of Patent: September 8, 1998
    Assignee: Elonex I.P. Holdings, Ltd.
    Inventors: Dan Kikinis, Pascal Dornier
  • Patent number: 5805901
    Abstract: A compressed I/O bus system for a general-purpose computer multiplexes 32 bit data and addresses on 32 of 42 dedicated parallel signal paths, and optimizes the bus structure by mapping bus requests made by peripheral devices to "high" memory portions of system RAM not dedicated to other purposes. In one aspect a bus controller is programmable to select translation routines stored in system RAM allowing various models and types of CPUs to be supported. Supported CPUs are interchangeable in the system. In another aspect a default interface attached to the compressed I/O bus of the invention, and translates bus states between the optimized compressed bus and one of an ISA bus or an EISA bus.
    Type: Grant
    Filed: November 12, 1996
    Date of Patent: September 8, 1998
    Assignee: Elonex I.P. Holdings Ltd.
    Inventors: Pascal Dornier, Dan Kikinis