Abstract: A printed circuit board (PCB) system includes an integrated circuit (IC) package having a main IC chip that is electrically coupled to a top surface of a package substrate. A first printed circuit board (PCB) is electrically coupled to first contact structures on a bottom surface of the package substrate. A heat dissipation member is coupled to the main IC chip. A memory module is configured to electrically couple, via an interposer, with second contact structures on a top surface of the package substrate while the heat dissipation member dissipates heat from the main IC chip away from one or more memory IC chips on the memory module. The interposer is configured to electrically couple the second contact structures of the IC package with the memory module while the heat dissipation member dissipates heat from the main IC chip away from the one or more memory IC chips.

Abstract: A source switching device in a switching system receives information measured by a target switching device in the switching system. The information is indicative of an amount of data received in a given amount of time by the target switching device via each of two or more first links coupled to the target switching device. The source switching device determines, based at least in part on the information received from the target device, a path, from among multiple paths from the source switching device to the target switching device, for transmission of a packet flow directed to the target switching device. The source switching device transmits, via the determined path for transmission of the packet flow to the target device, one or more packets belonging to the packet flow.

Abstract: A network device processes received packets to determine port or ports of the network device via which to transmit the packets. The network device classifies the packets into packet flows and selects, based at least in part on one or more characteristics of data being transmitted in the respective packet flows, a first packet memory having a first memory access bandwidth or a second packet memory having a second memory access bandwidth, and buffers the packets in the selected first or second packet memory which the packets are being processed by the network device. After processing the packets, the network device retrieves the packets from the first packet memory or the second packet memory in which the packets are buffered, and forwards the packets to the determined one or more ports for transmission of the packets.

Abstract: A packet processor of a network device receives packets ingressing from a plurality of network links via a plurality of network ports of the network device. The packet processor buffers the packets in an internal packet memory in a plurality of queues, including a first queue. In response to the packet processor detecting congestion in the internal packet memory, the packet processor selectively forwards a group of multiple packets in the first queue from the internal packet memory to a first port, among one or more ports coupled to one or more external memories, to transfer the group of multiple packets to a first external memory that is coupled to the first port so that the first queue is stored across the internal packet memory and the first external packet memory.

Abstract: A physical layer (PHY) processor of a network device receives a timing message via an external network and generates a first timestamp using a first local-domain clock used by the PHY processor. The PHY processor transfers the timing message and the first timestamp to a packet processor of the network device via an internal communication link. The packet processor generates a second timestamp for the timing message using a domain-specific clock. The packet processor determines a delay value using the first timestamp, the delay value accounting for a time delay corresponding to the transfer of the timing message within the network device from the PHY processor to the packet processor. The packet processor adjusts the second timestamp using the delay value to generate an adjusted domain-specific timestamp for the timing message.

Abstract: An integrated circuit package, including a circuit board, signal pins extending orthogonally to the circuit board surface, and grouped into a plurality of differential signal pin pairs, each signal pin pair positioned at a vertex of an array of orthogonal rows and columns, wherein each signal pin pair includes a positive and a negative signal pin. The plurality of signal pin pairs includes a first subset of signal pin pairs wherein the positive and the negative signal pins are arranged in an orientation along a line parallel to rows of the array and a second subset of signal pin pairs in which the positive and the negative signal pins are arranged in an orientation along a line parallel to columns of the array. For each signal pin pair in one of the first and second subsets, each nearest signal pin pairs belong to another of the first and second subsets.

Abstract: Methods and systems are provided for processing a received packet based on associated state information. A packet processor of a network device receives a packet from a network. The received packet is classified as belonging to at least one respective identified flow from among a plurality of identified flows. For a respective received packet that belongs to an identified flow a current state value for the identified flow is ascertained based on a state table. The current state value is assigned to the respective received packet based on the current state value using the state table for the identified flow. A packet processing operation is subsequently performed on the respective received packet based in part on the state value of the identified flow to which the respective packet belongs.

Abstract: A network device includes first, second, and third processors. The first processor detects congestion in a packet flow. The packet flow is i) one packet flow among a plurality of packet flows and ii) is formed of a plurality of packets of a same type received from a first device in a network via a first network connection. The packets in the packet flow are destined for a second device in the network. When congestion notification packet generation is enabled for the packet flow, the second processor generates a congestion notification packet by replicating a packet from the packet flow and sends the congestion notification packet to the first device via the first network connection. The congestion notification packet identifies the packet flow for which congestion is detected. The third processor forwards the plurality of packets in the packet flow to the second device via a second network connection.

Abstract: A network device includes a packet processor that: determines at least one egress port via which a received packet is to be transmitted by the network device; modifies one or more fields in a header of the packet to generate a modified header; determines, based at least in part on the modified header, whether the packet a) is to be transmitted or b) is to be discarded; and stores the modified header in a packet memory. In response to the determination that the packet is to be transmitted, a transmit processor of the network device: retrieves a payload of the packet from the packet memory; retrieves the modified header from the packet memory; generates a transmit packet at least by combining the payload of the packet with the modified header; and transmits the transmit packet via the determined at least one egress port of the network device.

Abstract: An integrated circuit (IC) is manufactured and is mounted in an IC package. A processor of a measurement system determines a reference value of a physical layer (PHY) parameter at a second test point on a test fixture based on one or more model values, specified by an Ethernet communication standard, corresponding to a first test point on the test fixture corresponding to a contact on the IC package and one or more measured test fixture parameters characterizing a channel connecting the first test point to the second test point on the test fixture. The processor then determines whether the PHY parameter at the first test point on the IC package complies with the Ethernet communication standard based on i) the reference value of the PHY parameter and ii) a measured value of the PHY parameter obtained from a measurement of the PHY parameter at the second test point.

Abstract: Electronic apparatus includes functional circuitry configured to respond to requests from a plurality of client devices, data storage circuitry configured as a plurality of client queues in which each respective client queue is configured to store pending requests from a respective client device, priority determination circuitry configured to assign a respective priority level to each respective client queue based at least in part on requests stored in the respective client queues, and arbiter circuitry configured to control access to the functional circuitry by the plurality of client devices. The arbiter circuitry is configured to monitor the priority level of each respective client queue, and control passage of requests from client queues to the functional circuitry based at least in part on a respective priority level assigned to each respective client queue. The priority determination circuitry includes fill level detector circuitry configured to determine a fill level of each client queue.

Abstract: A network device includes a rate measurement circuit that is configured to measure respective egress rates at which respective data is being transmitted via respective ports associated with the network device. A marking ratio determination circuit is configured to select respective marking ratios based on respective measured egress rates, the marking ratios for marking packets to be transmitted via the respective ports to indicate respective levels of congestion corresponding to the respective ports. Different marking ratios correspond to different measured egress rates. A packet editor circuit is configured to mark selected packets to be transmitted via respective ports according to the respective selected marking ratios. The respective selected marking ratios indicate to other communication devices that respective network paths via which the selected packets travelled experienced congestion, and the respective marking ratios indicate respective levels of congestion.

Abstract: A first solid state drive (SSD) includes a built-in network interface device configured to communicate via a network fabric, and a second SSD includes a built-in network interface device configured to communicate via the network fabric. A connection is opened between the first SSD and the second SSD over the network fabric, where the first SSD is further communicatively coupled to the second SSD further over an interconnect associated with a host computer. The first SSD encapsulates a non-volatile memory over fabric (NVMe-oF) command to transfer data between the first SSD and the second SSD in a capsule and sends the capsule to the second SSD over the connection. The second SSD executes the NVMe command to transfer the data between the first SSD and the second SSD over the connection according to an NVMe-oF communication protocol and without transferring any of the data to the host computer.

Abstract: A network device comprises a network interface configured to transmit packets via a network link, and timestamp circuitry configured to modify a packet that is to be transmitted by the network interface circuitry by embedding a future timestamp in the packet. The future timestamp corresponds to a transmit time at which the packet is to be transmitted by the network interface circuitry, and the transmit time occurs after the timestamp circuitry embeds the timestamp in the packet. Time gating circuitry is configured to i) receive the packet, ii) determine when a current time indicated by a clock circuit reaches the transmit time, iii) hold the packet from proceeding to the network interface circuitry prior to the current time reaching the transmit time, and iv) release the packet in response to the current time reaching the transmit time.

Abstract: In a switching system that comprises a central switching device an at least one port extender device, the central switching device includes at least one port configured to interface with the port extender device, and the port extender device includes a plurality of front ports for interfacing with one or more networks. The central switching device includes a processor that processes packets received from the at least one port extender device, and a plurality of egress queues for storing processed packets that are to be forwarded to the at least one port extender device for transmission via ones of the front ports. The central switching device also includes a flow control processor configured to, responsively to flow control messages received from the at least one port extender device, control transmission of packets to the at least one port extender device to prevent overflow of egress queues of the port extender device.

Abstract: A printed circuit board (PCB) system includes a first printed circuit board (PCB), an integrated circuit (IC) package, and a memory module. The IC package includes i) a package substrate, ii) a main IC chip that is electrically coupled to a top surface of the package substrate, iii) first contact structures that are disposed on a bottom surface of the package substrate and that are electrically coupled to the first PCB, and iv) second contact structures that are disposed on a top surface of the package substrate. The memory module includes i) a second PCB, ii) one or more memory IC chips that are disposed on the second PCB, and iii) third contact structures that are disposed on a bottom surface of the second PCB. An interposer electrically couples the second contact structures of the IC package with the third contact structures of the memory module.

Abstract: A media access control (MAC) processor of a network device receives a timing packet to be transmitted by the network device. The MAC processor generates one or more indicators to be used by a PHY device of the network device for embedding timing information into the timing packet. The one or more indicators include at least an indicator indicating that the timing packet is a type of packet into which timing information is to be embedded, an indicator of a location of a field in the timing packet at which the timing information is to be embedded, and an indicator of whether timing information in the timing packet needs to be updated. The MAC processor transfers the timing packet and the one or more indicators to the PHY device for further processing of the timing packet and subsequent transmission of the timing packet from the network device.

Abstract: A network device includes first, second, and third processors. The first processor detects congestion in a packet flow. The packet flow is i) one packet flow among a plurality of packet flows and ii) is formed of a plurality of packets of a same type received from a first device in a network via a first network connection. The packets in the packet flow are destined for a second device in the network. When congestion notification packet generation is enabled for the packet flow, the second processor generates a congestion notification packet by replicating a packet from the packet flow and sends the congestion notification packet to the first device via the first network connection. The congestion notification packet identifies the packet flow for which congestion is detected. The third processor forwards the plurality of packets in the packet flow to the second device via a second network connection.

Abstract: Packets received by a network switch device from upstream network devices, coupled to respective ones of a plurality of ports of the network switch device, are temporarily stored in an internal memory of the network switch device. In response to detecting congestion in the internal memory of the network switch device, a flow control engine triggers, during respective timeslots of a timing schedule and while the flow control engine continues to monitor congestion in the internal memory of the network switch device, transmission of respective flow control messages via different subsets of ports, among the plurality of ports, to control flow of packets from different subsets of upstream network device, among the plurality of upstream network devices, to the network switch device so that flow control is distributed over time among upstream network devices of the plurality of upstream network devices.

Abstract: Aspects of the disclosure provide a printed circuit board (PCB) system that includes an integrated circuit (IC) package, a first PCB and a PCB module. The IC package has a package substrate and an IC chip that is coupled to a top surface of the package substrate. The first PCB is configured to electrically couple with first contact structures that are disposed on a bottom surface of the package substrate. The PCB module includes a second PCB and one or more electronic components electrically coupled to the second PCB. The PCB module is configured to electrically couple with second contact structures that are disposed on the top surface of the package substrate.