Abstract: An indexing system provides a more efficient and effective interface to display and manipulate large amounts of trace data from computer data and storage networks that is captured and stored in the trace memory of a protocol analyzer. An index of the trace data in the trace memory is generated by reading a selected percentage of the trace data in the trace memory. Hardware circuitry selectively identifies locations in the trace memory of trace data for desired portions of the trace data. A processor utilizes the locations identified by the hardware circuitry to generate an index for the trace data stored in the trace memory. Preferably, the hardware circuitry searches for a first time stamp encountered in each of a series of blocks of trace data and the processor utilizes the first time stamps to build a time index for the series of blocks of trace data.

Abstract: An indexing system provides a more efficient and effective interface to display and manipulate large amounts of trace data from computer data and storage networks that is captured and stored in the trace memory of a protocol analyzer. An index of the trace data in the trace memory is generated by reading a selected granularity percentage of the trace data in the trace memory. A host processor connected to the protocol analyzer generates at least two graphic representations on a computer display device of the trace data in response to and based on the index. A first graphic representation is generated by setting the selected granularity percentage at a first percentage and a second graphic representation similar to the first graphic representation generated while the first graphic representation is being displayed by setting the selected percentage at a second percentage that is greater than the first percentage to regenerate the index.

Abstract: An integrated multi-channel Fiber Channel analyzer provides coordinated and cooperative triggering and capture of data across multiple channels in a Fiber Channel network. The integrated multi-channel analyzer accommodates up to sixteen separate analyzer channels in a single cabinet. Each analyzer channel is comprised of an input port connection to the Fiber Channel network, a trace buffer memory that captures data and logic circuitry that controls the operation of the trace buffer memory in response to a status condition. A high speed status bus is connected to each analyzer channel and propagates the status conditions of each analyzer channel to all other analyzer channels. In this way, the integrated multi-channel analyzer allows for distributive control over triggering decisions across multiple analyzer channels, and also allows for multi-level triggering where different conditions may be detected by different analyzer channels.

Abstract: A deep trace buffer management system for a protocol analyzer includes a hardware search engine that locates specified data patterns within the trace buffer as directed by a host processor. The protocol analyzer is preferably connected to a laptop computer that serves as the host processor, and the protocol analyzer preferably is housed in a portable chassis separate from the host processor and has a host port to connect to the host processor through a relatively small bandwidth port. An interface port connects the protocol analyzer to the communication interface under analysis. Logic circuitry controls selective read and write operations of traces to and from the trace buffer in response to parameters as directed by the host processor.

Abstract: A deep trace buffer management system for a protocol analyzer includes a hardware search engine that locates specified data patterns within the trace buffer as directed by a host processor. The protocol analyzer is preferably connected to a laptop computer that serves as the host processor, and the protocol analyzer preferably is housed in a portable chassis separate from the host processor and has a host port to connect to the host processor through a relatively small bandwidth port. An interface port connects the protocol analyzer to the communication interface under analysis. Logic circuitry controls selective read and write operations of traces to and from the trace buffer in response to parameters as directed by the host processor.

Abstract: A deep trace buffer management system for a protocol analyzer includes a hardware search engine that locates specified data patterns within the trace buffer as directed by a host processor. The protocol analyzer is preferably connected to a laptop computer that serves as the host processor, and the protocol analyzer preferably is housed in a portable chassis separate from the host processor and has a host port to connect to the host processor through a relatively small bandwidth port. An interface port connects the protocol analyzer to the communication interface under analysis. Logic circuitry controls selective read and write operations of traces to and from the trace buffer in response to parameters as directed by the host processor.

Abstract: A universal electrical interface system connects to a small computer system interface (SCSI) bus. In a passive embodiment, a set of single-ended receivers and a set of differential receivers receive electrical signals on the SCSI bus according to the single-ended or differential protocol, respectively, when each set of receivers is enabled. In an active embodiment, a set of single-ended transceivers and a set of differential transceivers transmit and receive electrical signals on the SCSI bus according to the single-ended or differential protocol, respectively, when each set of transceivers is enabled. A control mechanism connected to both sets of receivers or transceivers automatically determines whether the SCSI bus is configured to use either the single-ended or differential parallel interface protocol and selectively enables the set of single ended receivers or transceivers, or the set of differential receivers or transceivers.

Abstract: A universal electrical interface system connects to a small computer system interface (SCSI) bus. In a passive embodiment, a set of single-ended receivers and a set of differential receivers receive electrical signals on the SCSI bus according to the single-ended or differential protocol, respectively, when each set of receivers is enabled. In an active embodiment, a set of single-ended transceivers and a set of differential transceivers transmit and receive electrical signals on the SCSI bus according to the single-ended or differential protocol, respectively, when each set of transceivers is enabled. A control mechanism connected to both sets of receivers or transceivers automatically determines whether the SCSI bus is configured to use either the single-ended or differential parallel interface protocol and selectively enables the set of single ended receivers or transceivers, or the set of differential receivers or transceivers.

Abstract: A software architecture and method for controlling multi-thread peripheral operations in an initiator device such as a computer equipped with a SCSI interface. A data structure is provided for storage of thread context parameters. High level code places a low level driver in either a single-thread or multi-thread mode, and then issues peripheral commands by calling the low level driver. The low level driver manages the interface protocol, returning to the high level code when a command is complete, or if in multi-thread mode, when a command disconnects. Management of the data structure is accomplished by the low level driver, minimizing the impact of multi-thread operations on the high level code.