Abstract: An ion implantation system for producing silicon wafers having relatively low defect densities, e.g., below about 1×106/cm2, includes a fluid port in the ion implantation chamber for introducing a background gas into the chamber during the ion implantation process. The introduced gas, such as water vapor, reduces the defect density of the top silicon layer that is separated from the buried silicon dioxide layer.

Abstract: A wafer holder assembly includes first and second main structural members from which first and second wafer-holding arms extend. The first arm is secured to the main structural members by a graphite distal retaining member. The second arm is pivotally biased to a wafer-hold position by a graphite bias member. This arrangement provides a conductive path from the wafer to the assembly for inhibiting electrical discharges from the wafer during the ion implantation process. The assembly can further include additional graphite retaining members for maintaining the structural integrity of the assembly during the extreme conditions associated with SIMOX wafer processing without the need for potentially wafer-contaminating adhesives and conventional fasteners. The wafer-contacting pins at the distal end of the arms can be formed from silicon. The silicon pins can be coated with titanium nitride to enhance electrical contact with the wafer and to provide an abrasion resistant surface.

Abstract: The present invention provides a method for creation of high quality semiconductor-on-insulator structures, e.g., silicon-on-insulator structures, using implantation of sub-stoichiometric doses of oxygen at multiple energies. The method employs sequential steps of ion implantation and high temperature annealing to produce structures with a top silicon layer having a thickness ranging from 10-250 nm and a buried oxide layer having a thickness 30-300 nm. The buried oxide layer has a breakdown field greater than 5 MV/cm. Further, the density of silicon inclusions in the BOX region is less than 2×107 cm−2. The process of the invention can be used to create an entire SOI wafer, or be used to create patterned SOI, regions where SOI regions are integrated with non-SOI regions.