Abstract: A method and apparatus teaching insertion of addressing indirection to form and to access an array hierarchy expressly permitting the concurrency of a high level RAID array, the bandwidth and degraded mode operation sustainable by a lower level RAID array, and after a DASD failure minimum spanning involvement when the array is rebuilding and rewriting missing data to a spare logical device. Also, disclosed are the accessing of variable length records on the array hierarchy; array hierarchy in which RAID 5 arrays have dissimilar number of logic devices (lower level RAID arrays) and interleave depths; formation of logical arrays using fractional storage defined onto real DASD subsets; and the defining of logical devices onto DASDs distributed in the same or different physical clusters of DASDs and the rebuild operation thereof.
Type:
Grant
Filed:
July 3, 1991
Date of Patent:
April 5, 1994
Assignee:
IBM Corp. (International Business Machines Corp.)
Inventors:
Jaishankar M. Menon, Leighton C. Wood, Jr.