Abstract: Via holes are formed in an electrically conductive power plane. Photo-imageable dielectric (PID) material is applied to one side of the power plane filling the via holes. The power plane side with no PID material is exposed to light energy to cure the PID material in the via holes. A developer is used to remove any uncured PID material. Signal plane assemblies comprising a conductive signal plane and a dielectric layer are laminated onto the filled power plane forming a two signal and one power plane (2S1P) structure. In another embodiment, the power plane has PID material applied from both sides. A photo-mask is applied to the power plane and the PID material in the via holes is cured with light energy. A developer is used to remove uncured PID material. Signal plane assemblies, as described above, are laminated onto the filled power plane forming a 2S1P structure.
Type:
Application
Filed:
April 23, 2003
Publication date:
October 9, 2003
Applicant:
IBM Corporation
Inventors:
Anilkumar C. Bhatt, Ashwinkumar C. Bhatt, Subahu D. Desai, John M. Lauffer, Voya R. Markovich, Thomas R. Miller
Abstract: Methods, systems and computer program products are provided for which associate physical links of a network device to aggregator ports of the network device where there are more physical links of the network device capable of aggregation than aggregator ports of the network device. Physical links are associated with the aggregator ports of the network device based on a session invariant characteristic of the physical links until either all of the aggregator ports of the network device have been associated with physical links or all of the physical links capable of aggregation have been associated with an aggregator port. The remaining physical links are then utilized as single links to the network device irrespective of the physical link's capability to aggregate.
Type:
Grant
Filed:
May 27, 1999
Date of Patent:
October 7, 2003
Assignee:
IBM Corporation
Inventors:
Arush Kumar, Loren Douglas Larsen, Jeffrey James Lynch
Abstract: The present invention provides a temperature programmable timing delay system utilizing circuitry for generating a band-gap reference and for sensing the on-chip temperature of an integrated circuit chip. The circuitry outputs the sensed temperature as a binary output which is received by a programmable table circuit of the timing delay system. The programmable table circuit outputs a binary output corresponding to the received binary output. The timing delay system further includes a temperature dependent timing delay circuit having inputs for receiving the binary output of the programmable table circuit and an output for outputting a timing delay signal for delaying a clock by a timing delay corresponding to the binary output of the programmable table circuit. The band-gap reference can be a temperature independent band-gap reference voltage having a constant-voltage value or a temperature dependent band-gap reference current having a constant-current value.
Type:
Grant
Filed:
January 5, 2001
Date of Patent:
October 7, 2003
Assignee:
IBM Corporation
Inventors:
Louis L. Hsu, Rajiv V. Joshi, John A. Fifield
Abstract: A memory system having a plurality of T-RAM cells arranged in an array is presented where each T-RAM cell has dual vertical devices and is fabricated over a SiC substrate. Each T-RAM cell has a vertical thyristor and a vertical transfer gate. The top surface of each thyristor is coplanar with the top surface of each transfer gate within the T-RAM array to provide a planar cell structure for the T-RAM array. A method is also presented for fabricating the T-RAM array having the vertical thyristors, the vertical transfer gates and the planar cell structure over the SiC substrate.
Abstract: The present invention provides a pad system for an integrated circuit or device. The pad system includes logic circuitry having at least one pad input terminal for connecting to at least one pad and at least two output terminals for connecting to the at least one circuit system of the integrated circuit or device. The logic circuitry is configurable to selectively connect the at least one pad between at least two points of the at least one circuit system of the integrated circuit or device.
Type:
Grant
Filed:
January 3, 2002
Date of Patent:
September 16, 2003
Assignee:
IBM Corporation
Inventors:
Louis L. Hsu, Li-Kong Wang, Chorng-Lii Hwang
Abstract: Novel interconnect structures possessing a relatively low internal stress and dielectric constant for use in semiconductor devices are provided herein. The novel interconnect structures comprise a first layer having a coefficient of thermal expansion greater than about 20 ppm and a first internal stress associated therewith, the first layer having a first set of metallic lines formed therein; a second layer having a coefficient of thermal expansion less than about 20 ppm and a second internal stress associated therewith, the second layer having a second set of metallic lines formed therein; and one or more stress adjustment cap layers formed between the first layer and the second layer, the cap layer(s) having a third internal stress to offset the first stress of the first layer and the second stress of the second layer and inducing a favorable relief of stress on the interconnect structure. Methods for making a semiconductor device having a substantially reduced internal stress are also provided.
Type:
Grant
Filed:
August 14, 2002
Date of Patent:
September 9, 2003
Assignee:
IBM Corporation
Inventors:
Stephen M. Gates, Timothy J. Dalton, John A. Fitzsimmons
Abstract: The present invention provides for globally aligning microelectronic circuit systems, such as communication devices and chips, fabricated on or bonded to the front and back sides of one or more substrates to provide for wireless communications between the circuit systems through the one or more substrates. In one embodiment, two circuit systems situated on opposite sides of a substrate are aligned to provide for wireless communications between the two circuit systems through the substrate. In another embodiment, communication devices situated on one or more substrates are aligned to provide for wireless communications between the communication devices through the one or more substrates. In another embodiment, two chips situated on opposite sides of a transparent substrate are aligned to provide for wireless communications between the two chips through the transparent substrate.
Type:
Grant
Filed:
January 25, 2001
Date of Patent:
September 9, 2003
Assignee:
IBM Corporation
Inventors:
Louis L. Hsu, Rajiv V. Joshi, Carl Radens, Jack A. Mandelman, Tsorng-Dih Yuan
Abstract: A system and method is provided for real time teleconferencing, where one of the participants is deaf or hearing-impaired. In one aspect of the system and method, each participant has an Automatic Speech Recognition (ASR) system and a chat service system, such as AOL Instant Messenger™. Each participant may have a different type of ASR system, as well as a different type of chat service system. It is not necessary that the deaf or hearing-impaired participant have an ASR system. For each participant, the participant's ASR system transcribes the speech of the participant and provides it to the participant's chat service system, which translates the transcribed text into the chat service message in the format of the participant's chat service system.
Type:
Grant
Filed:
December 1, 2000
Date of Patent:
September 9, 2003
Assignee:
IBM Corporation
Inventors:
Dimitri Kanevsky, Sara H. Basson, Edward Adam Epstein, Peter G. Fairweather
Abstract: A data clock system for a semiconductor memory system is provided for performing reliable high-speed data transfers. The semiconductor memory system includes a plurality of data banks configured for storing data, the plurality of data banks in operative communication with a plurality of first data paths, each first data path in operative communication with a second data path. The data clock system includes a first clock path receiving a clock signal during a data transfer operation for transferring data between one data bank of the plurality of data banks and the second data path via one of the plurality of first data paths; and a second clock path receiving the clock signal from the first clock path and propagating the clock signal along therethrough, the second clock path including at least one clock driver. The transfer of data between the one of the plurality of first data paths and the second data path occurs upon receipt of the clock signal by the at least one clock driver.
Type:
Grant
Filed:
January 22, 2002
Date of Patent:
September 2, 2003
Assignee:
IBM Corporation
Inventors:
Louis L. Hsu, Jeremy K. Stephens, Daniel W. Storaska, Li-Kong Wang
Abstract: A micromachined electromechanical random access memory (MEMRAM) array is disclosed which includes a plurality of MEM memory cells, where each MEM memory cell has an MEM switch and a capacitor. The MEM switch includes a contact portion configured for moving from a first position to a second position for reading out a charge stored within the capacitor or for writing the charge to the capacitor. A method is also disclosed for fabricating each MEM memory cell of the MEMRAM array.
Abstract: A trainable radio scanner, including a station monitoring circuit to scan a plurality of radio frequencies and extract audio samples of a predetermined duration from each one of the plurality of radio frequencies having a signal strength above a reception threshold; a memory storing audio classification data and the plurality of audio samples; and an audio analyzer to analyze each one of the plurality of audio samples using the audio classification data and classifies each audio sample into a musical style category; a style discriminator to control a radio station scanning operation of the radio receiver to tune only to preferred radio stations having a radio frequency at which the corresponding audio sample is classified in at least one preferred musical style category.
Abstract: Methods and arrangements for facilitating data clustering. From a set of input data, a predetermined number of non-overlapping subsets are created. The input data is split recursively to create the subsets.
Type:
Application
Filed:
January 4, 2002
Publication date:
August 21, 2003
Applicant:
IBM Corporation
Inventors:
Upendra V. Chaudhari, Jiri Navratil, Ganesh N. Ramaswamy
Abstract: The present invention is a method and system that enables reference processes that have access to a long running object to maintain the current access to this object while this object performs a re-initialization operation in order to refresh data contained in the object. The system of the invention comprises a long running object manager that controls the re-initialization process of an object registered with the object manager. In operation, a reference program establishes a connection to the long running for purposes of accessing information in the object. This connection to the object is noted in the object manager. At this point, during the connection of the reference to the long running object, there is an event to trigger a re-initialization of the long running object. The object manager notifies the object of the trigger and holds the references that are connected to this object. The object receives the re-initialization signal, performs the re-initialization and sends a reply to the object manager.
Abstract: Path-based ranking of unvisited Web pages for WWW crawling is provided, via identifying all the paths beginning with a “seed” URL and leading to visited relevant web pages as “good-path set”, and for each unvisited web page, identifying the paths beginning from the “seed” URL leading to it as “partial-path set”; classifying all the visited web pages and labeling each web Page with the labels of a class or classes it belongs to; training a statistic model for generalizing the common patterns among all ones of “good-path set”; and evaluating the “partial-path set” with the statistic model and ranking the unvisited web pages with the evaluation results.
Abstract: The present invention provides an improved method, an system, and a set of computer implemented instructions for handling a cache containing multiple single-bit hard errors on multiple addresses within a data processing system. Such handles will prevent any down time by logging in the parts to be replaced by an operator when certain level of bit errors is reached. When a hard error exists on a cache address for the first time, serviceable first hard error, that cache line is deleted. Thus the damaged memory device is no longer used by the system. As a result, the system is running with “N−x” lines wherein “N” constitutes the total number of existing lines and “x” is less than “N”. An alternative method is to exchange the damaged memory device to a spare memory device. In order to provide such services, the system must first differentiate whether an error is a soft or hard error.
Type:
Application
Filed:
January 30, 2002
Publication date:
July 31, 2003
Applicant:
IBM Corporation
Inventors:
James Stephen Fields, ALongkorn Kitamorn, Wayne Lemmon, David Otto Lewis, Kevin F. Reick
Abstract: A method, system, and computer program product for resolving address information in an ad-hoc networking environment. Two indicators are defined to indicate whether (1) a device has a self-assigned (i.e. auto-configured) IP (Internet Protocol) address and (2) the device has an administered IP address (i.e. an IP address configured by an administrator or assigned by a service such as a Dynamic Host Configuration Protocol service). These indicators are communicated, along with a device's IP host name, IP address, subnet, and subnet mask, preferably as augmented information of existing protocol messages. The information may be communicated during establishment of the data link layer connection between two devices, or it may be communicated during service discovery protocol exchanges between two devices, or in a combination thereof.
Abstract: A method of ad hoc data sharing for virtual teams rooms, including creating at least one user record representing a user granted access to digital assets, wherein each user has a client device, at least two of the client devices are wirelessly coupled for data communications to at least one computer, and each user record comprises a user access privilege field identifying for each user that user's user access privilege for access to digital assets. Embodiments also include receiving from client devices digital asset records representing digital assets, retrieving digital assets in dependence upon the location fields in the digital asset records, displaying the retrieved digital assets, and editing one or more of the retrieved digital assets, wherein the editing is carried out in dependence upon user access privilege and in dependence upon asset access permission.
Abstract: A demodulator which includes an active balun circuit and at least one mixer driven by the active balun circuit. The active balun circuit includes a negative shunt feedback arrangement.
Abstract: Methods and arrangements for facilitating speaker identification. At least one N-best list is generated based on input speech, a system output is posited based on the input speech, and a determination is made, via at least one property of the N-best list, as to whether the posited system output is inconclusive.
Type:
Application
Filed:
January 4, 2002
Publication date:
July 10, 2003
Applicant:
IBM Corporation
Inventors:
Upendra V. Chaudhari, Jiri Navratil, Ganesh N. Ramaswamy