Abstract: A method that includes forming a first level of active circuitry on a substrate, forming a first probe pad electrically connected to the first level of active circuitry where the first probe pad having a first surface, contacting the first probe pad with a probe tip that displaces a portion of the first probe pad above the first surface, and performing a chemical mechanical polish on the first probe pad to planarize the portion of the first probe pad above the first surface. The method also includes forming a second level of active circuitry overlying the first probe pad, forming a second probe pad electrically connected to the second level of active circuitry, contacting the second probe pad with a probe tip that displaces a portion of the probe pad, and chemically mechanically polishing the second probe pad to remove the portion displaced.
Type:
Application
Filed:
September 14, 2012
Publication date:
March 21, 2013
Applicants:
IBM SEMICONDUCTOR RESEARCH AND DEVELOPMENT CENTER (SRDC), STMICROELECTRONICS, INC.
Inventors:
John H. Zhang, Laertis Economikos, Robin Van Den Nieuwenhuizen, Wei-Tsu Tseng
Abstract: A method that includes forming a first level of active circuitry on a substrate, forming a first probe pad electrically connected to the first level of active circuitry where the first probe pad having a first surface, contacting the first probe pad with a probe tip that displaces a portion of the first probe pad above the first surface, and performing a chemical mechanical polish on the first probe pad to planarize the portion of the first probe pad above the first surface. The method also includes forming a second level of active circuitry overlying the first probe pad, forming a second probe pad electrically connected to the second level of active circuitry, contacting the second probe pad with a probe tip that displaces a portion of the probe pad, and chemically mechanically polishing the second probe pad to remove the portion displaced.
Type:
Application
Filed:
September 13, 2012
Publication date:
March 14, 2013
Applicants:
IBM Semiconductor Research and Development Center (SRDC), STMicroelectronics, Inc.
Inventors:
John H. Zhang, Laertis Economikos, Robin Van Den Nieuwenhuizen, Wei-Tsu Tseng
Abstract: A method that includes forming a first level of active circuitry on a substrate, forming a first probe pad electrically connected to the first level of active circuitry where the first probe pad having a first surface, contacting the first probe pad with a probe tip that displaces a portion of the first probe pad above the first surface, and performing a chemical mechanical polish on the first probe pad to planarize the portion of the first probe pad above the first surface. The method also includes forming a second level of active circuitry overlying the first probe pad, forming a second probe pad electrically connected to the second level of active circuitry, contacting the second probe pad with a probe tip that displaces a portion of the probe pad, and chemically mechanically polishing the second probe pad to remove the portion displaced.
Type:
Application
Filed:
December 31, 2009
Publication date:
June 30, 2011
Applicants:
STMICROELECTRONICS, INC., IBM Semiconductor Research and Development Center (SRDC)
Inventors:
John H. Zhang, Laertis Economikos, Robin Van Den Nieuwenhuizen, Wei-Tsu Tseng