Abstract: An apparatus has a semiconductor wafer hosting rows and columns of chips, where the rows and columns of chips are separated by scribe lines. Vertical and horizontal routing lines are in the scribe lines interconnecting the rows and columns of chips. Test circuit sites are in the scribe lines, each test circuit site including contact pads for simultaneous connection to probe card needles, sensor circuit select and control circuitry, and a sensor circuit bank.
Type:
Grant
Filed:
June 24, 2022
Date of Patent:
November 26, 2024
Assignee:
IC ANALYTICA, LLC
Inventors:
Patrick G. Drennan, Joseph S. Spector, Richard Wunderlich
Abstract: An apparatus has a semiconductor wafer hosting rows and columns of chips, where the rows and columns of chips are separated by scribe lines. Voltage regulators are positioned within the scribe lines. Each voltage regulator is connected to one or more chips. Selection circuitry is positioned within the scribe lines. The selection circuitry governs access to a chip being tested.
Type:
Grant
Filed:
June 24, 2022
Date of Patent:
June 11, 2024
Assignee:
IC ANALYTICA, LLC
Inventors:
Patrick G. Drennan, Joseph S. Spector, Richard Wunderlich