Abstract: Systems, methods, and devices relating to the provision of deliberate predistortion to an input signal to compensate for distortions introduced by an amplifier subsystem. An input signal is received by a predistortion subsystem which applies deliberate predistortions to the input signal to arrive at a predistorted signal. The predistorted signal is received by an amplifier subsystem which decomposes the signal, processes the decomposed signal, and then recombines the components to arrive at a system output signal. The predistortion subsystem adaptively adjusts the predistortions based on characteristics of the system output signal. A feedback signal, a replica of the system output signal, is used in updating lookup table entries used to determine the predistortion.

Abstract: Embodiments of the present invention include systems and methods for optimizing the transmitter and receiver weights of a MIMO system. In one embodiment, the weights are optimized to create and steer beam nulls, such that each transmitted signal is substantially decoupled from all other signals between a MIMO transmitter a MIMO receiver. In another embodiment, the weights are selected such that, the signal strength of each weighted signal transmitted through a communications channel along a respective signal path is substantially equivalent, but for which the weighting vectors are not necessarily orthogonal. In a further embodiment, each transmitted signal is coupled only between its own transmitter and receiver antennas with a gain, or eigenvalue, that is a consequence of the weights, and which is bounded to within a desired range of values while at the same time the weighing vectors are orthogonal. Embodiments employing various decomposition techniques are also provided.

Abstract: Embodiments of the present invention include systems and methods for optimizing the transmitter and receiver weights of a MIMO system. In one embodiment, the weights are optimized to create and steer beam nulls, such that each transmitted signal is substantially decoupled from all other signals between a MIMO transmitter a MIMO receiver. In another embodiment, the weights are selected such that, the signal strength of each weighted signal transmitted through a communications channel along a respective signal path is substantially equivalent, but for which the weighting vectors are not necessarily orthogonal. In a further embodiment, each transmitted signal is coupled only between its own transmitter and receiver antennas with a gain, or eigenvalue, that is a consequence of the weights, and which is bounded to within a desired range of values while at the same time the weighing vectors are orthogonal. Embodiments employing successive decomposition are also provided.

Abstract: Embodiments of the present invention comprise methods and devices for amplifying a signal by amplifying a first signal and by then amplifying a second signal only if the first signal exceeds a predetermined threshold. The first and second amplified signals are then combined, and the combination is fed back to a signal source and used to control the values of the first and second signal. The combination is further transmitted to a load. In the preferred embodiment, the first amplified signal is transmitted through an impedance inverter before it is combined with the second amplified signal.

Abstract: The present invention comprises systems, methods, and devices for detecting the presence of a specified signal type by autocorrelating the signal with a time-delayed copy of itself, by simultaneously crosscorrelating the signal with an expected signal type, and by then comparing the results of the autocorrelation and crosscorrelation to determine whether or not the signal is present and to ascertain its type.

Abstract: Systems and methods relating to the provision of gain, phase and delay adjustments to signals to be used by a predistortion subsystem. A portion of an input signal is delayed by delay elements prior to being received by the predistortion subsystem. The delayed input signal portion is also received by a feedback signal processing subsystem that adjusts the gain and phase of the feedback signal based on the delayed input signal portion. The adjusted feedback signal is used, along with the delayed portion of the input signal, to determine an appropriate predistortion modification to be applied to the input signal.

Abstract: A switched-mode Class F power amplifier is provided for parallel connection with at least one other like amplifier, within a Chireix architecture, for combining the signals output therefrom. An input component includes at least one active device configured to be alternately switched by a signal input thereto to present an amplified signal corresponding to the input signal and constituting a low output impedance voltage source. A lumped element impedance inverter is provided between the input component and an output resonator component, the impedance inverter being configured for transforming the low output impedance voltage source to instead constitute a high output impedance current source configured for said parallel connection. In accordance with the invention, the negative reactive component values required by the impedance inverter are eliminated and effectively provided by incorporating those values into pre-selected reactive components of the input and output components.

Abstract: A switched-mode power amplifier is configured for performing power amplification of a plurality of signals input thereto and integrally summing (combining) those signals. Conceptually, this is achieved by replacing the input winding of the transformer component of a transformer-coupled voltage switching amplifier with separate input components, one for each input signal, in similar manner to the configuration of the input components of a three-port combiner (trifilar). In a first transformer-containing category of embodiments of the invention, the input winding of the amplifier's transformer is comprised of a plurality of series-coupled windings, one for each of the plurality of input components/signals such that the input components constitute a series connection of low output impedance sources applied to the amplifier's resonator and load. This, in turn, provides a high level of isolation between the amplifier input components and results in a low level of loss.

Abstract: Embodiments of the present invention comprise systems, methods, and devices for amplifying electromagnetic signals by decomposing each signal into a plurality of near-constant envelope signals, removing residual amplitude modulation from these signals, amplifying each signal independently, and recombining the amplified signals. In the preferred embodiment a plurality of control signals, each corresponding to the magnitude of a respective near-constant envelope signal, is employed to amplify each near-constant envelope signal in inverse proportion to its corresponding control signal. This inverse amplification preferably eliminates any unwanted residual amplitude modulation thus producing an amplified constant envelope signal. The plurality of amplified constant envelope signals is then preferably combined to form an amplified version of the incoming signal.

Abstract: The present invention relates to wireless communications and is particularly applicable to devices and modules for correcting errors introduced to a wireless signal after its transmission. An equalizer is provided which compensates for undesirable effects on received radio signals introduced by either signal processing or by the transmission medium. In operation, the equalizer multiples the complex received signal with a complex corrective signal that compensates for these effects. A tap corrective signal corrects for time-varying channel effects (i.e. channel distortions), a timing tracking signal corrects for carrier frequency offset errors, and a phase tracking signal corrects for sampling frequency offset errors.

Abstract: The invention relates to the field of electronics, more particularly to the wire bonds incorporated into an integrated circuit package such as a quad flat pack, a ball grid array or hybrid style module. The present invention takes the normally undesirable wire bond inductance and uses it in an operational circuit where positive inductance is required. The circuit in which the wire bond inductance is used is located primarily in the integrated circuit die housed in the integrated circuit package, but may also include off-die components. In one example, a wire bond is used as the required series inductance in a discrete circuit impedance inverter which consists of two shunt-to-ground negative inductances and one series positive inductance. One of the negative inductances is located on-die, while the other is located off-die.

Abstract: The invention relates to the field of wireless communications, more particularly to a method of and device for switching between antennae in communication with a diversity receiver, each of the antennae receiving signals transmitted from a single source. A packet from a transmitter is received by respective antenna communicating with a diversity receiver. The signal strength of the preamble of the packet received in a first antenna is sampled. If the signal strength is of sufficient magnitude to affect reliable reception, the associated antenna is selected for the duration of the packet transmission. If the signal strength is below a predetermined threshold the signal strength of the preamble of the packet received in a second antenna is sampled and compared to the sample associated with the first antenna. If the magnitude of the second sample is greater, the signal associated with the second antenna is selected.

Abstract: Circuits and methods for use in amplifying amplitude and phase modulated signals. A circuit uses a combiner with dual parallel signal amplifiers feeding it. The signal amplifiers have a low output impedance while the combiner does not provide any isolation between its inputs from the signal amplifiers. As in other Chireix architectures, the signals from the signal amplifiers are phase modulated prior to being fed to the combiner. The combiner then combines these two signals and, depending on how these two signals are combined, the resulting output of the combiner is amplitude modulated. The signal amplifiers may be Class D or Class F amplifiers to provide high efficiency amplification of the signals.

Abstract: Systems and modules for use in trellis-based decoding of convolutionally encoded sets of data bits. A first calculation module receives an encoded set of data bits and calculates a signal distance or a measure of the differences between the encoded set and each one of a group of predetermined states, each state being represented by a sequence of data bits. The first calculation module consists of multiple parallel calculation submodules with each submodule being tasked to perform an XOR operation between the encoded set and one of the predetermined states. Multiple parallel second calculation modules each multiple receiving the output of the first calculation module, calculates cumulative signal distances using the output of the first calculation module. Each second calculation module has multiple parallel addition submodules with each addition submodule receiving a specific cumulative signal distance and one of the signal distances calculated by the first calculation.

Abstract: Systems and modules for use in trellis-based decoding of encoded sets of data bits. A memory system has multiple arrays for storing an index for each one of multiple states. With each array element being associated with a state through which a decoding path may pass through, the contents of each array element is an index which points to an immediately preceding state. This immediately preceding state is represented by another array element in another array. Each array is populated with array element entries as encoded data set are received by a separate decoder which generates the indices. For every given number of arrays in a group, a trace-back process traces back the path followed by an encoding procedure for encoding the encoded set. By tracing back this path through the various arrays, the original unencoded set of data bits can be found.

Abstract: Circuits and methods for use in amplifying amplitude and phase modulated signals. A circuit uses a combiner with dual parallel signal amplifiers feeding it. The signal amplifiers have a low output impedance while the combiner does not provide any isolation between its inputs from the signal amplifiers. As in other Chireix architectures, the signals from the signal amplifiers are phase modulated prior to being fed to the combiner. The combiner then combines these two signals and, depending on how these two signals are combined, the resulting output of the combiner is amplitude modulated. The signal amplifiers may be Class D or Class F amplifiers to provide high efficiency amplification of the signals.

Abstract: An improvement for a phasor fragmentation engine and method, whereby a phasor flipping algorithm is applied when determining fragment phasors for a non-constant envelope modulation signal (e.g. OFDM). The phasor flipping algorithm avoids sharp phase transitions for the fragment phasors, which cause an increase in bandwidth, by performing a comparison of the phasor angle separation between the prior and current time samples. This comparison corresponds to a determination of whether the modulation signal V has passed near or through zero.

Abstract: Systems, methods and devices for scrambling/descrambling sets of data bits using subsets of a recurring sequence of scrambler bits. A self-synchronous scrambler, regardless of the generating polynomial being implemented, will generate repeating sequences of scrambler bits regardless of the initial stage of the scrambler. To implement a parallel scrambler, given a current state of the scrambler, the next n states of the scrambler are predicted based on the current state of the scrambler. The scrambling operation can then be preformed using the values in the current state—parallel logic operations between preselected bits of the current state will yield the required values to be used in scrambling an incoming parallel data set. Once these required values are generated, a parallel logical operation between the required values and the incoming data set will result in the scrambled output data.

Abstract: A switched-mode power amplifier is configured for performing power amplification of a plurality of signals input thereto and integrally summing (combining) those signals. Conceptually, this is achieved by replacing the input winding of the transformer component of a transformer-coupled voltage switching amplifier with separate input components, one for each input signal, in similar manner to the configuration of the input components of a three-port combiner (trifilar). In a first transformer-containing category of embodiments of the invention, the input winding of the amplifier's transformer is comprised of a plurality of series-coupled windings, one for each of the plurality of input components/signals such that the input components constitute a series connection of low output impedance sources applied to the amplifier's resonator and load. This, in turn, provides a high level of isolation between the amplifier input components and results in a low level of loss.

Abstract: Methods and devices for encoding in parallel a set of data bits for use in communications systems. The set of data bits to be encoded is divided into two subsets with the first subset being encoded in parallel using the second subset. The first subset is also encoded in parallel using the second subset. The first subset is also encoded in parallel using a subset of an immediately preceding set of data bits. Parallel encoding is realized by using an encoding module utilizing multiple single bit submodule. Each submodule receives a single bit from the first subset and either the second subset or the subset of the immediately preceding data set. Each single bit submodule produces a pair of output bits from the convolutional encoding of a single bit of the first subset and either the second subset of the subset of the immediately preceding data set. The multiple single bit submodules operate in parallel to simultaneously and collectively produce a set of data bits.