Abstract: One embodiment of the present includes a heterogeneous, high-performance, scalable processor having at least one W-type sub-processor capable of processing W bits in parallel, W being an integer value, at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value smaller than W by a factor of two. The processor further includes a shared bus coupling the at least one W-type sub-processor and at least one N-type sub-processor and memory shared coupled to the at least one W-type sub-processor and the at least one N-type sub-processor, wherein the W-type sub-processor rearranges memory to accommodate execution of applications allowing for fast operations.
Abstract: A system, method and computer program product for processing payments, including a server in an electronic device and/or a server in a remote location; a database in the electronic device and/or a database in a remote location coupled to the respective server; and an electronic device of a consumer coupled to the server over a communications network, wherein the server is configured to determine a payment option most advantageous to the consumer based on information stored in the database regarding a plurality of payment options available to the consumer, and the server is configured to display the most advantageous payment option to the consumer on the electronic device of the consumer.
Type:
Application
Filed:
June 16, 2012
Publication date:
August 21, 2014
Applicant:
ICELERO INC
Inventors:
Amit Ramchandran, Amir Masoud Zarkesh, Saeid Ghafouri
Abstract: One embodiment of the present includes a heterogeneous, high-performance, scalable processor having at least one W-type sub-processor capable of processing W bits in parallel, W being an integer value, at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value smaller than W by a factor of two. The processor further includes a shared bus coupling the at least one W-type sub-processor and at least one N-type sub-processor and memory shared coupled to the at least one W-type sub-processor and the at least one N-type sub-processor, wherein the W-type sub-processor rearranges memory to accommodate execution of applications allowing for fast operations.