Patents Assigned to IceMos Technology Limited
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Publication number: 20230369403Abstract: A high voltage superjunction MOSFET includes a semiconductor substrate and a semiconductor layer having columns of first and second conductivity. A buffer layer of the first conductivity is between the semiconductor substrate and semiconductor layer. A plug region of the second conductivity is formed at a semiconductor layer surface and extends to the columns. A source/drain region is formed at the semiconductor layer surface and is connected to the plug region. The source/drain region has a concentration of the first conductivity between about 1×1019 cm?3 and 1.5×1020 cm?3. A body region of the second conductivity is between the source/drain region and the first column and is connected to the plug region. A gate trench is formed in the semiconductor layer surface and extends toward the first column and has a trench gate electrode disposed therein. A dielectric layer separates the trench gate electrode from the first column.Type: ApplicationFiled: July 25, 2023Publication date: November 16, 2023Applicant: IceMos Technology LimitedInventors: Kiraneswar Muthuseenu, Samuel Anderson, Takeshi Ishiguro
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Publication number: 20230207568Abstract: A power transistor has a plurality of cells, each cell having a notch formed in a substrate. An insulating material, such as an oxide, is formed within the notch. A semiconductor layer is formed over the substrate and insulating material. The semiconductor layer has a first type of semiconductor material and a second type of semiconductor material opposite the first type of semiconductor material to form the power transistor. A width of the insulating material within the notch is less than a width of the semiconductor layer so that a portion of the substrate extends to the semiconductor layer. The notch can have a slope or a step. The insulating material has a first thickness and a second thickness greater than the first thickness within the notch. The insulating material may extend completely across the interface between substrate and semiconductor layer, or only partially across the interface.Type: ApplicationFiled: December 21, 2022Publication date: June 29, 2023Applicant: IceMos Technology LimitedInventors: Takeshi Ishiguro, Samuel J. Anderson, Aymeric Privat
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Publication number: 20230154977Abstract: A semiconductor device has a substrate and semiconductor layer formed over the substrate. A trench is formed through the semiconductor layer. An insulating material is disposed in the trench. A first column of semiconductor material having a first conductivity type extends through the semiconductor layer adjacent to the trench. A second column of semiconductor material having a second conductivity type extends through the semiconductor layer adjacent to the first column of semiconductor material. A first insulating layer is formed between the insulating material and a side surface of the trench. A source region is formed within the semiconductor layer. A gate region is formed adjacent to the insulating layer. A second insulating layer is formed between the gate region and source region. A conductive layer is formed over the semiconductor layer. The source region is coupled to the conductive layer.Type: ApplicationFiled: October 7, 2022Publication date: May 18, 2023Applicant: IceMos Technology LimitedInventors: Takeshi Ishiguro, Aymeric Privat, Samuel J. Anderson
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Publication number: 20230154976Abstract: A semiconductor device has a substrate and semiconductor layer formed over the substrate. A trench is formed through the semiconductor layer. A polysilicon material is disposed in the trench. A first column of semiconductor material having a first conductivity type extends through the semiconductor layer adjacent to the trench. A second column of semiconductor material having a second conductivity type extends through the semiconductor layer adjacent to the first column of semiconductor material. A conductive layer is formed over the semiconductor layer. The polysilicon material is coupled to the conductive layer and operates as a field plate. A first insulating layer is formed between the polysilicon material and a side surface of the trench. A source region is formed within the semiconductor layer. A gate region is formed adjacent to the insulating layer. A second insulating layer is formed between the gate region and source region.Type: ApplicationFiled: October 7, 2022Publication date: May 18, 2023Applicant: IceMos Technology LimitedInventors: Takeshi Ishiguro, Aymeric Privat, Samuel J. Anderson
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Publication number: 20230061775Abstract: A semiconductor device has a substrate made of a first semiconductor material. The first semiconductor material is silicon carbide. A first semiconductor layer made of the first semiconductor material is disposed over the substrate. A second semiconductor layer made of a second semiconductor material dissimilar from the first semiconductor material is disposed over the first semiconductor layer. The second semiconductor material is silicon. A third semiconductor layer made of the second semiconductor material can be disposed between the first semiconductor layer and second semiconductor layer. A semiconductor device or electrical component is formed in the second semiconductor layer. The electrical component can be a power MOSFET. A first insulating layer, such as an oxide layer, is formed over the electrical component, and second insulating layer, such as a nitride layer, is formed over the first insulating layer for protection against radiation.Type: ApplicationFiled: August 25, 2022Publication date: March 2, 2023Applicant: IceMos Technology LimitedInventors: Samuel J. Anderson, Takeshi Ishiguro, Cathal Duffy, Aymeric Privat
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Publication number: 20230067511Abstract: A semiconductor device has a substrate. The substrate can be multiple layers. A first semiconductor layer made of a first semiconductor material is disposed over the substrate. The first semiconductor material can be substantially defect-free silicon carbide. A second semiconductor layer made of a second semiconductor material dissimilar from the first semiconductor material is disposed over the first semiconductor layer. The second semiconductor material is silicon. A third layer can be disposed between the first semiconductor layer and second semiconductor layer. A semiconductor device is formed in the second semiconductor layer. The semiconductor device can be a power MOSFET or diode. The second semiconductor layer with the electrical component provides a first portion of a breakdown voltage for the semiconductor device and the first semiconductor layer and substrate provide a second portion of the breakdown voltage for the semiconductor device.Type: ApplicationFiled: August 25, 2022Publication date: March 2, 2023Applicant: IceMos Technology LimitedInventors: Samuel J. Anderson, Takeshi Ishiguro, Cathal Duffy, Aymeric Privat
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Publication number: 20230060866Abstract: A semiconductor device has a first substrate and a first semiconductor layer having a first semiconductor material formed over the first substrate. A surface of the first semiconductor layer has a first element of the first semiconductor material. A first surface of a second semiconductor layer having the first semiconductor material is joined to the surface of the first semiconductor layer. The first surface of the second semiconductor layer has a second element of the first semiconductor material different from the first element. The first semiconductor material is silicon carbide or cubic silicon carbide. The first element is silicon or carbon, and the second element is carbon or silicon. The semiconductor device provides characteristics of radiation hardening. A third semiconductor layer is formed over a second surface of the second semiconductor layer opposite the first surface. An electrical component is formed over the second semiconductor layer.Type: ApplicationFiled: August 24, 2022Publication date: March 2, 2023Applicant: IceMos Technology LimitedInventors: Samuel J. Anderson, Takeshi Ishiguro, Cathal Duffy, Aymeric Privat
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Publication number: 20230061047Abstract: A semiconductor device has a first substrate made of a first semiconductor material, such as silicon. A sacrificial layer is formed over a first surface of the first substrate. A seed layer is formed over the sacrificial layer. A compliant layer is formed over a second surface of the first substrate opposite the first surface of the first substrate. A first semiconductor layer made of a second semiconductor material, such as silicon carbide, dissimilar from the first semiconductor material is formed over the sacrificial layer. The first substrate and sacrificial layer are removed leaving the first semiconductor layer substantially defect-free. The first semiconductor layer containing the second semiconductor material is formed at a temperature greater than a melting point of the first semiconductor material. A second semiconductor layer is formed over the first semiconductor layer with an electrical component formed in the second semiconductor layer.Type: ApplicationFiled: July 11, 2022Publication date: March 2, 2023Applicant: IceMos Technology LimitedInventors: Aymeric Privat, Takeshi Ishiguro, Cathal Duffy, Samuel J. Anderson
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Publication number: 20230064236Abstract: A semiconductor device has a substrate made of a first semiconductor material. The first semiconductor material is silicon carbide. A first semiconductor layer made of the first semiconductor material is disposed over the substrate. A second semiconductor layer made of a second semiconductor material dissimilar from the first semiconductor material is disposed over the first semiconductor layer. The first semiconductor material is substantially defect-free silicon carbide, and the second semiconductor material is silicon. A semiconductor device is formed in the second semiconductor layer. The semiconductor device can be a power MOSFET, diode, insulated gate bipolar transistor, cluster trench insulated gate bipolar transistor, and thyristor. The second semiconductor layer with the electrical component provides a first portion of a breakdown voltage for the semiconductor device and the first semiconductor layer and substrate provide a second portion of the breakdown voltage for the semiconductor device.Type: ApplicationFiled: August 25, 2022Publication date: March 2, 2023Applicant: IceMos Technology LimitedInventors: Samuel J. Anderson, Takeshi Ishiguro, Cathal Duffy, Aymeric Privat
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Publication number: 20230065348Abstract: A semiconductor device has a substrate made of a first semiconductor material. The first semiconductor material is silicon carbide. A first semiconductor layer made of the first semiconductor material is disposed over the substrate. A second semiconductor layer made of a second semiconductor material dissimilar from the first semiconductor material is disposed over the first semiconductor layer. The second semiconductor material is silicon. A third semiconductor layer made of the second semiconductor material can be disposed between the first semiconductor layer and second semiconductor layer. A semiconductor device is formed in the second semiconductor layer. The semiconductor device can be a power MOSFET or diode. The second semiconductor layer with the electrical component provides a first portion of a breakdown voltage for the semiconductor device and the first semiconductor layer and substrate provide a second portion of the breakdown voltage for the semiconductor device.Type: ApplicationFiled: August 25, 2022Publication date: March 2, 2023Applicant: IceMos Technology LimitedInventors: Samuel J. Anderson, Takeshi Ishiguro, Cathal Duffy, Aymeric Privat
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Publication number: 20220293733Abstract: A high voltage superjunction MOSFET includes a semiconductor substrate and a semiconductor layer having columns of first and second conductivity. A buffer layer of the first conductivity is between the semiconductor substrate and semiconductor layer. A plug region of the second conductivity is formed at a semiconductor layer surface and extends to the columns. A source/drain region is formed at the semiconductor layer surface and is connected to the plug region. The source/drain region has a concentration of the first conductivity between about 1×1019 cm?3 and 1.5×1020 cm?3. A body region of the second conductivity is between the source/drain region and the first column and is connected to the plug region. A gate trench is formed in the semiconductor layer surface and extends toward the first column and has a trench gate electrode disposed therein. A dielectric layer separates the trench gate electrode from the first column.Type: ApplicationFiled: May 27, 2022Publication date: September 15, 2022Applicant: IceMos Technology LimitedInventors: Kiraneswar Muthuseenu, Samuel Anderson, Takeshi Ishiguro
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Publication number: 20220236261Abstract: An atomic level deposition for mass functionalization of a cavity filled with a pathogen sensitive antibody reagent to functionalize each Biosensor using atomic level vapor phase deposition enables high volume production of this sensor technology. A biosensor has a first substrate and a second substrate with a cavity formed in the first substrate to form a membrane. Holes is formed through the second substrate. An aluminum oxide layer is formed over the cavity and into the holes to form cores. The cavity is filled with a pathogen sensitive antibody reagent. A biofluid sample with the pathogen is deposited over the membrane. The biofluid is drawn through the cores to mix with the antibody reagent. The antibodies combine with the pathogen to change the impedance along the current path. The presence of the pathogen changes the ionic current flow through the biosensor for a positive detection of the pathogen.Type: ApplicationFiled: January 26, 2021Publication date: July 28, 2022Applicant: IceMos Technology LimitedInventors: Samuel J. Anderson, Hugh J. Griffin
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Publication number: 20220236214Abstract: An atomic level deposition for mass functionalization of a cavity filled with a pathogen sensitive antibody reagent to functionalize each biosensor using atomic level vapor phase deposition enables high volume production of this sensor technology. A biosensor has a first substrate and a second substrate with a cavity formed in the first substrate to form a membrane. Holes are formed through the second substrate. An aluminum oxide layer is formed over the cavity and into the holes to form cores. The cavity is filled with a pathogen sensitive antibody reagent. A biofluid sample with the pathogen is deposited over the membrane. The biofluid is drawn through the cores to mix with the antibody reagent. The antibodies combine with the pathogen to change the impedance along the current path. The presence of the pathogen changes the ionic current flow through the biosensor for a positive detection of the pathogen.Type: ApplicationFiled: February 9, 2021Publication date: July 28, 2022Applicant: IceMos Technology LimitedInventors: Samuel J. Anderson, Hugh J. Griffin
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Publication number: 20220123134Abstract: A semiconductor device has a substrate and graphene with semiconducting properties or diamond region formed on the substrate. The graphene with semiconducting properties or diamond region is formed on or within the substrate using liquid-phase-epitaxy growth of graphene enabled by a catalytic alloy of Ni and Cu. The substrate can be silicon, silicon carbide, gallium arsenide, gallium nitride, germanium, or indium phosphide. A semiconductor component is formed over the graphene with semiconducting properties or diamond region and substrate. The semiconductor component can be a power MOSFET, IGBT, or CTIGBT with a gate structure formed over the substrate, source region adjacent to the gate structure, and drain region adjacent to the gate structure opposite the source region. The graphene with semiconducting properties or diamond region is formed under a gate of the MOSFET to reduce drain to source resistance, as well as providing radiation hardening for the device.Type: ApplicationFiled: October 21, 2020Publication date: April 21, 2022Applicant: IceMos Technology LimitedInventor: Samuel J. Anderson