Patents Assigned to IceMos Technology Limited
  • Publication number: 20260262272
    Abstract: A semiconductor device has a substrate. The substrate can be multiple layers. A first semiconductor layer made of a first semiconductor material is disposed over the substrate. The first semiconductor material can be substantially defect-free silicon carbide. A second semiconductor layer made of a second semiconductor material dissimilar from the first semiconductor material is disposed over the first semiconductor layer. The second semiconductor material is silicon. A third layer can be disposed between the first semiconductor layer and second semiconductor layer. A semiconductor device is formed in the second semiconductor layer. The semiconductor device can be a power MOSFET or diode. The second semiconductor layer with the electrical component provides a first portion of a breakdown voltage for the semiconductor device and the first semiconductor layer and substrate provide a second portion of the breakdown voltage for the semiconductor device.
    Type: Application
    Filed: April 22, 2026
    Publication date: September 3, 2026
    Applicant: IceMos Technology Limited
    Inventors: Samuel J. Anderson, Takeshi Ishiguro, Cathal Duffy, Aymeric Privat
  • Patent number: 12727450
    Abstract: A semiconductor device has a first substrate made of a first semiconductor material, such as silicon. A sacrificial layer is formed over a first surface of the first substrate. A seed layer is formed over the sacrificial layer. A compliant layer is formed over a second surface of the first substrate opposite the first surface of the first substrate. A first semiconductor layer made of a second semiconductor material, such as silicon carbide, dissimilar from the first semiconductor material is formed over the sacrificial layer. The first substrate and sacrificial layer are removed leaving the first semiconductor layer substantially defect-free. The first semiconductor layer containing the second semiconductor material is formed at a temperature greater than a melting point of the first semiconductor material. A second semiconductor layer is formed over the first semiconductor layer with an electrical component formed in the second semiconductor layer.
    Type: Grant
    Filed: July 11, 2022
    Date of Patent: September 1, 2026
    Assignee: IceMos Technology Limited
    Inventors: Aymeric Privat, Takeshi Ishiguro, Cathal Duffy, Samuel J. Anderson
  • Publication number: 20260206266
    Abstract: A semiconductor device has a substrate made of a first semiconductor material. The first semiconductor material is silicon carbide. A first semiconductor layer made of the first semiconductor material is disposed over the substrate. A second semiconductor layer made of a second semiconductor material dissimilar from the first semiconductor material is disposed over the first semiconductor layer. The second semiconductor material is silicon. A third semiconductor layer made of the second semiconductor material can be disposed between the first semiconductor layer and second semiconductor layer. A semiconductor device is formed in the second semiconductor layer. The semiconductor device can be a power MOSFET or diode. The second semiconductor layer with the electrical component provides a first portion of a breakdown voltage for the semiconductor device and the first semiconductor layer and substrate provide a second portion of the breakdown voltage for the semiconductor device.
    Type: Application
    Filed: March 11, 2026
    Publication date: July 16, 2026
    Applicant: IceMos Technology Limited
    Inventors: Samuel J. Anderson, Takeshi Ishiguro, Cathal Duffy, Aymeric Privat
  • Patent number: 12635200
    Abstract: A semiconductor device has a substrate. The substrate can be multiple layers. A first semiconductor layer made of a first semiconductor material is disposed over the substrate. The first semiconductor material can be substantially defect-free silicon carbide. A second semiconductor layer made of a second semiconductor material dissimilar from the first semiconductor material is disposed over the first semiconductor layer. The second semiconductor material is silicon. A third layer can be disposed between the first semiconductor layer and second semiconductor layer. A semiconductor device is formed in the second semiconductor layer. The semiconductor device can be a power MOSFET or diode. The second semiconductor layer with the electrical component provides a first portion of a breakdown voltage for the semiconductor device and the first semiconductor layer and substrate provide a second portion of the breakdown voltage for the semiconductor device.
    Type: Grant
    Filed: August 25, 2022
    Date of Patent: May 19, 2026
    Assignee: IceMos Technology Limited
    Inventors: Samuel J. Anderson, Takeshi Ishiguro, Cathal Duffy, Aymeric Privat
  • Publication number: 20260129923
    Abstract: A semiconductor device has a substrate and semiconductor layer formed over the substrate. A trench is formed through the semiconductor layer. A polysilicon material is disposed in the trench. A first column of semiconductor material having a first conductivity type extends through the semiconductor layer adjacent to the trench. A second column of semiconductor material having a second conductivity type extends through the semiconductor layer adjacent to the first column of semiconductor material. A conductive layer is formed over the semiconductor layer. The polysilicon material is coupled to the conductive layer and operates as a field plate. A first insulating layer is formed between the polysilicon material and a side surface of the trench. A source region is formed within the semiconductor layer. A gate region is formed adjacent to the insulating layer. A second insulating layer is formed between the gate region and source region.
    Type: Application
    Filed: December 30, 2025
    Publication date: May 7, 2026
    Applicant: IceMos Technology Limited
    Inventors: Takeshi Ishiguro, Aymeric Privat, Samuel J. Anderson
  • Patent number: 12598782
    Abstract: A semiconductor device has a substrate made of a first semiconductor material. The first semiconductor material is silicon carbide. A first semiconductor layer made of the first semiconductor material is disposed over the substrate. A second semiconductor layer made of a second semiconductor material dissimilar from the first semiconductor material is disposed over the first semiconductor layer. The second semiconductor material is silicon. A third semiconductor layer made of the second semiconductor material can be disposed between the first semiconductor layer and second semiconductor layer. A semiconductor device is formed in the second semiconductor layer. The semiconductor device can be a power MOSFET or diode. The second semiconductor layer with the electrical component provides a first portion of a breakdown voltage for the semiconductor device and the first semiconductor layer and substrate provide a second portion of the breakdown voltage for the semiconductor device.
    Type: Grant
    Filed: August 25, 2022
    Date of Patent: April 7, 2026
    Assignee: IceMOS Technology Limited
    Inventors: Samuel J. Anderson, Takeshi Ishiguro, Cathal Duffy, Aymeric Privat
  • Publication number: 20260076108
    Abstract: A semiconductor device has a substrate made of a first semiconductor material. The first semiconductor material is silicon carbide. A first semiconductor layer made of the first semiconductor material is disposed over the substrate. A second semiconductor layer made of a second semiconductor material dissimilar from the first semiconductor material is disposed over the first semiconductor layer. The first semiconductor material is substantially defect-free silicon carbide, and the second semiconductor material is silicon. A semiconductor device is formed in the second semiconductor layer. The semiconductor device can be a power MOSFET, diode, insulated gate bipolar transistor, cluster trench insulated gate bipolar transistor, and thyristor. The second semiconductor layer with the electrical component provides a first portion of a breakdown voltage for the semiconductor device and the first semiconductor layer and substrate provide a second portion of the breakdown voltage for the semiconductor device.
    Type: Application
    Filed: November 18, 2025
    Publication date: March 12, 2026
    Applicant: IceMos Technology Limited
    Inventors: Samuel J. Anderson, Takeshi Ishiguro, Cathal Duffy, Aymeric Privat
  • Patent number: 12527043
    Abstract: A semiconductor device has a substrate and semiconductor layer formed over the substrate. A trench is formed through the semiconductor layer. A polysilicon material is disposed in the trench. A first column of semiconductor material having a first conductivity type extends through the semiconductor layer adjacent to the trench. A second column of semiconductor material having a second conductivity type extends through the semiconductor layer adjacent to the first column of semiconductor material. A conductive layer is formed over the semiconductor layer. The polysilicon material is coupled to the conductive layer and operates as a field plate. A first insulating layer is formed between the polysilicon material and a side surface of the trench. A source region is formed within the semiconductor layer. A gate region is formed adjacent to the insulating layer. A second insulating layer is formed between the gate region and source region.
    Type: Grant
    Filed: October 7, 2022
    Date of Patent: January 13, 2026
    Assignee: IceMOS Technology Limited
    Inventors: Takeshi Ishiguro, Aymeric Privat, Samuel J. Anderson
  • Patent number: 12506006
    Abstract: A semiconductor device has a substrate made of a first semiconductor material. The first semiconductor material is silicon carbide. A first semiconductor layer made of the first semiconductor material is disposed over the substrate. A second semiconductor layer made of a second semiconductor material dissimilar from the first semiconductor material is disposed over the first semiconductor layer. The first semiconductor material is substantially defect-free silicon carbide, and the second semiconductor material is silicon. A semiconductor device is formed in the second semiconductor layer. The semiconductor device can be a power MOSFET, diode, insulated gate bipolar transistor, cluster trench insulated gate bipolar transistor, and thyristor. The second semiconductor layer with the electrical component provides a first portion of a breakdown voltage for the semiconductor device and the first semiconductor layer and substrate provide a second portion of the breakdown voltage for the semiconductor device.
    Type: Grant
    Filed: August 25, 2022
    Date of Patent: December 23, 2025
    Assignee: IceMos Technology Limited
    Inventors: Samuel J. Anderson, Takeshi Ishiguro, Cathal Duffy, Aymeric Privat
  • Publication number: 20250157813
    Abstract: A semiconductor device has a first substrate and a first semiconductor layer formed over the first substrate. A second substrate is disposed over a surface of the first semiconductor layer opposite the first substrate. The first semiconductor layer and second semiconductor layer can be silicon carbide or cubic silicon carbide. The first substrate and a portion of the first semiconductor layer are removed to reduce defects in the first semiconductor layer. A second semiconductor layer is formed over a remaining portion of the first semiconductor layer. A third semiconductor layer is disposed over the second semiconductor layer. The third semiconductor layer can be silicon. The third semiconductor layer can be disposed over the second semiconductor layer by direct wafer bonding. An electrical component is formed within the third semiconductor layer. The electrical component can be a power MOSFET, IGBT, CTIGBT, diode, and thyristor.
    Type: Application
    Filed: November 12, 2024
    Publication date: May 15, 2025
    Applicant: IceMos Technology Limited
    Inventors: Samuel J. Anderson, Takeshi Ishiguro, Cathal Duffy
  • Patent number: 12230674
    Abstract: A high voltage superjunction MOSFET includes a semiconductor substrate and a semiconductor layer having columns of first and second conductivity. A buffer layer of the first conductivity is between the semiconductor substrate and semiconductor layer. A plug region of the second conductivity is formed at a semiconductor layer surface and extends to the columns. A source/drain region is formed at the semiconductor layer surface and is connected to the plug region. The source/drain region has a concentration of the first conductivity between about 1×1019 cm?3 and 1.5×1020 cm?3. A body region of the second conductivity is between the source/drain region and the first column and is connected to the plug region. A gate trench is formed in the semiconductor layer surface and extends toward the first column and has a trench gate electrode disposed therein. A dielectric layer separates the trench gate electrode from the first column.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: February 18, 2025
    Assignee: IceMos Technology Limited
    Inventors: Kiraneswar Muthuseenu, Samuel Anderson, Takeshi Ishiguro
  • Patent number: 12222316
    Abstract: An atomic level deposition for mass functionalization of a cavity filled with a pathogen sensitive antibody reagent to functionalize each biosensor using atomic level vapor phase deposition enables high volume production of this sensor technology. A biosensor has a first substrate and a second substrate with a cavity formed in the first substrate to form a membrane. Holes are formed through the second substrate. An aluminum oxide layer is formed over the cavity and into the holes to form cores. The cavity is filled with a pathogen sensitive antibody reagent. A biofluid sample with the pathogen is deposited over the membrane. The biofluid is drawn through the cores to mix with the antibody reagent. The antibodies combine with the pathogen to change the impedance along the current path. The presence of the pathogen changes the ionic current flow through the biosensor for a positive detection of the pathogen.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: February 11, 2025
    Assignee: IceMos Technology Limited
    Inventors: Samuel J. Anderson, Hugh J. Griffin
  • Publication number: 20240405067
    Abstract: A semiconductor device has a substrate and semiconductor layer formed over the substrate. The semiconductor layer has a first conductivity type. A trench is formed through the semiconductor layer. A semiconductor material having a second conductivity type is deposited over a side surface of the trench by vapor phase deposition or plasma doping. The semiconductor material is diffused into the semiconductor layer to form a first column of semiconductor material having the second conductivity type within the semiconductor layer. A first insulating layer is formed over the side surface of the trench. A body region is formed within the semiconductor layer. A source region is formed within the body region. A gate region is formed within the body region. A second insulating layer is formed over the trench. A third insulating layer is formed over the second insulating layer. A conductive layer is formed over the third insulating layer.
    Type: Application
    Filed: March 31, 2024
    Publication date: December 5, 2024
    Applicant: IceMos Technology Limited
    Inventors: Samuel J. Anderson, Takeshi Ishiguro
  • Publication number: 20240405068
    Abstract: A semiconductor device has a substrate and semiconductor layer formed over the substrate. The semiconductor layer has a first conductivity type. A trench is formed through the semiconductor layer. An epitaxial layer having a second conductivity type is formed over a surface of the semiconductor layer and a side surface of the trench. The epitaxial layer is diffused into the semiconductor layer to form a first column of semiconductor material having the second conductivity type within the semiconductor layer. A first insulating layer is formed over the side surface of the trench. A body region is formed within the semiconductor layer. A source region is formed within the body region. A gate region is formed within the body region. A second insulating layer is formed over the trench. A third insulating layer is formed over the second insulating layer. A conductive layer is formed over the third insulating layer.
    Type: Application
    Filed: March 31, 2024
    Publication date: December 5, 2024
    Applicant: IceMos Technology Limited
    Inventors: Samuel J. Anderson, Takeshi Ishiguro
  • Publication number: 20230369403
    Abstract: A high voltage superjunction MOSFET includes a semiconductor substrate and a semiconductor layer having columns of first and second conductivity. A buffer layer of the first conductivity is between the semiconductor substrate and semiconductor layer. A plug region of the second conductivity is formed at a semiconductor layer surface and extends to the columns. A source/drain region is formed at the semiconductor layer surface and is connected to the plug region. The source/drain region has a concentration of the first conductivity between about 1×1019 cm?3 and 1.5×1020 cm?3. A body region of the second conductivity is between the source/drain region and the first column and is connected to the plug region. A gate trench is formed in the semiconductor layer surface and extends toward the first column and has a trench gate electrode disposed therein. A dielectric layer separates the trench gate electrode from the first column.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 16, 2023
    Applicant: IceMos Technology Limited
    Inventors: Kiraneswar Muthuseenu, Samuel Anderson, Takeshi Ishiguro
  • Publication number: 20230207568
    Abstract: A power transistor has a plurality of cells, each cell having a notch formed in a substrate. An insulating material, such as an oxide, is formed within the notch. A semiconductor layer is formed over the substrate and insulating material. The semiconductor layer has a first type of semiconductor material and a second type of semiconductor material opposite the first type of semiconductor material to form the power transistor. A width of the insulating material within the notch is less than a width of the semiconductor layer so that a portion of the substrate extends to the semiconductor layer. The notch can have a slope or a step. The insulating material has a first thickness and a second thickness greater than the first thickness within the notch. The insulating material may extend completely across the interface between substrate and semiconductor layer, or only partially across the interface.
    Type: Application
    Filed: December 21, 2022
    Publication date: June 29, 2023
    Applicant: IceMos Technology Limited
    Inventors: Takeshi Ishiguro, Samuel J. Anderson, Aymeric Privat
  • Publication number: 20230154977
    Abstract: A semiconductor device has a substrate and semiconductor layer formed over the substrate. A trench is formed through the semiconductor layer. An insulating material is disposed in the trench. A first column of semiconductor material having a first conductivity type extends through the semiconductor layer adjacent to the trench. A second column of semiconductor material having a second conductivity type extends through the semiconductor layer adjacent to the first column of semiconductor material. A first insulating layer is formed between the insulating material and a side surface of the trench. A source region is formed within the semiconductor layer. A gate region is formed adjacent to the insulating layer. A second insulating layer is formed between the gate region and source region. A conductive layer is formed over the semiconductor layer. The source region is coupled to the conductive layer.
    Type: Application
    Filed: October 7, 2022
    Publication date: May 18, 2023
    Applicant: IceMos Technology Limited
    Inventors: Takeshi Ishiguro, Aymeric Privat, Samuel J. Anderson
  • Publication number: 20230154976
    Abstract: A semiconductor device has a substrate and semiconductor layer formed over the substrate. A trench is formed through the semiconductor layer. A polysilicon material is disposed in the trench. A first column of semiconductor material having a first conductivity type extends through the semiconductor layer adjacent to the trench. A second column of semiconductor material having a second conductivity type extends through the semiconductor layer adjacent to the first column of semiconductor material. A conductive layer is formed over the semiconductor layer. The polysilicon material is coupled to the conductive layer and operates as a field plate. A first insulating layer is formed between the polysilicon material and a side surface of the trench. A source region is formed within the semiconductor layer. A gate region is formed adjacent to the insulating layer. A second insulating layer is formed between the gate region and source region.
    Type: Application
    Filed: October 7, 2022
    Publication date: May 18, 2023
    Applicant: IceMos Technology Limited
    Inventors: Takeshi Ishiguro, Aymeric Privat, Samuel J. Anderson
  • Publication number: 20230061775
    Abstract: A semiconductor device has a substrate made of a first semiconductor material. The first semiconductor material is silicon carbide. A first semiconductor layer made of the first semiconductor material is disposed over the substrate. A second semiconductor layer made of a second semiconductor material dissimilar from the first semiconductor material is disposed over the first semiconductor layer. The second semiconductor material is silicon. A third semiconductor layer made of the second semiconductor material can be disposed between the first semiconductor layer and second semiconductor layer. A semiconductor device or electrical component is formed in the second semiconductor layer. The electrical component can be a power MOSFET. A first insulating layer, such as an oxide layer, is formed over the electrical component, and second insulating layer, such as a nitride layer, is formed over the first insulating layer for protection against radiation.
    Type: Application
    Filed: August 25, 2022
    Publication date: March 2, 2023
    Applicant: IceMos Technology Limited
    Inventors: Samuel J. Anderson, Takeshi Ishiguro, Cathal Duffy, Aymeric Privat
  • Publication number: 20230065348
    Abstract: A semiconductor device has a substrate made of a first semiconductor material. The first semiconductor material is silicon carbide. A first semiconductor layer made of the first semiconductor material is disposed over the substrate. A second semiconductor layer made of a second semiconductor material dissimilar from the first semiconductor material is disposed over the first semiconductor layer. The second semiconductor material is silicon. A third semiconductor layer made of the second semiconductor material can be disposed between the first semiconductor layer and second semiconductor layer. A semiconductor device is formed in the second semiconductor layer. The semiconductor device can be a power MOSFET or diode. The second semiconductor layer with the electrical component provides a first portion of a breakdown voltage for the semiconductor device and the first semiconductor layer and substrate provide a second portion of the breakdown voltage for the semiconductor device.
    Type: Application
    Filed: August 25, 2022
    Publication date: March 2, 2023
    Applicant: IceMos Technology Limited
    Inventors: Samuel J. Anderson, Takeshi Ishiguro, Cathal Duffy, Aymeric Privat