Abstract: Method for tuning a Single Sideband receiver including processing the signal in the time domain, converting the signal to the frequency domain, processing the signal in the frequency domain, converting the modified signal from the frequency domain to a correlation domain, processing the signal in the correlation domain and analyzing the processed signal from the correlation domain to determine a receiver tuning error.

Abstract: Method for tuning a Single Sideband receiver including processing the signal in the time domain, converting the signal to the frequency domain, processing the signal in the frequency domain, converting the modified signal from the frequency domain to a correlation domain, processing the signal in the correlation domain and analyzing the processed signal from the correlation domain to determine a receiver tuning error.

Abstract: Frequency synthesizer utilizing fractional-N synthesis includes a phase detector having an input receivable of a reference frequency, a loop filter arranged to receive the signal from the phase detector, a tunable oscillator arranged to receive a tuning signal generated by the loop filter and provide an output frequency and an integer divider arranged to receive the output frequency of the oscillator, divide it by a division control number (N+F) and provide the divided output frequency to the phase detector. The division control number is made up of an integer (N) and a fraction portion (F) separated into at least two different fractions. The fraction portion is generated by at least two sigma-delta converters, each processing a respective fraction with the sigma-delta converter processing a smaller fraction being driven at a lower clock rate than a sigma-delta converter processing the largest fraction.

Abstract: Frequency synthesizer utilizing fractional-N synthesis includes a phase detector having an input receivable of a reference frequency, a loop filter arranged to receive the signal from the phase detector, a tunable oscillator arranged to receive a tuning signal generated by the loop filter and provide an output frequency and an integer divider arranged to receive the output frequency of the oscillator, divide it by a division control number (N+F) and provide the divided output frequency to the phase detector. The division control number is made up of an integer (N) and a fraction portion (F) separated into at least two different fractions. The fraction portion is generated by at least two sigma-delta converters, each processing a respective fraction with the sigma-delta converter processing a smaller fraction being driven at a lower clock rate than a sigma-delta converter processing the largest fraction.