Abstract: An improved programmable logic device comprises a mixed mode programmable logic array in which a group of product terms generated by a programmable AND array are both fixedly connected to a group of OR gates and selectively connected to a programmable OR array. All the outputs of the OR gates and the programmable OR array are fed to a programmable multiplexer which provides a set of outputs of the device. The OR array is split into two sub OR arrays connected by a programmable OR array connection bit line to offer more flexibility. This structure mixes programmable OR array and fixed OR array together and provides the device with fast speed performance as well as high logic mapping flexibility and logic utilization.