Abstract: An apparatus for relaying a terrestrial broadcast signal includes a broadcast receiving unit configured to receive a broadcast signal from a terrestrial broadcast station via a over-the-air broadcast network and a broadcast streaming unit configured to stream the broadcast signal to a display terminal via a wireless communication network.

Abstract: A method of installing a terrestrial broadcast signal relay apparatus having a wireless communication function includes connecting the broadcast signal relay apparatus and a mobile terminal having a GPS function with a wireless communication network, determining a location of the broadcast signal relay apparatus based on a location of the mobile terminal obtained by using the GPS function, determining a location of a nearest broadcast transmission tower based on the location of the broadcast signal relay apparatus, and determining an optimal location for installing the broadcast signal relay apparatus in a room based on the location of the nearest broadcast transmission tower.

Abstract: A programmable logic device (PLD) includes logic built-in blocks (LBB) connected with a programmable interconnection array (PIA). Each LBB has two configurable logic cells sharing a group of control product terms, which serve as global and local control signals. Each configurable logic cell employs a programmable array (an AND gate array connected to two OR gate arrays), followed by two groups of Multi-Register Macro Cells (MRMC). The multi-register macro cells contain registers, which are grouped into logic control cells, multiplexers and I/O cells. The registers receive sum terms from the OR gate arrays as inputs, while the multiplexers direct the flow of the outputs and feedbacks, which can be either latched outputs from registers or direct sum terms from the OR gate arrays. All of the controls of the multi-register macro cells in an LBB are available from shared control product terms, thus providing both local and global control signals.

Abstract: A structure and method for high density programmable logic device (PLD) testing, programming, and verification is disclosed. The device employs non-volatile memory cells, such as electrically erasable programmable ROM (EEPROM), as its programmable elements. The structure and method allow the PLD to work in the normal operation state and also in a number of utility states. In normal operation state, the PLD performs the configured logic function as programmed by the user. In utility states, the PLD can be programmed, verified and tested. A state machine and a decoder are used to perform these procedures. They include bit program (write), verify (read), bulk program (write all), bulk erase (erase all), checker board and inverse checker board program, cell current test, address decode test, softwrite test and logical function test data preload. All the utilities are in a serial algorithm and are controlled by an internal state machine, which needs as few as four dedicated pins to interface with the PLD proper.