Abstract: A current sense amplifier for an Erasable Programmable read only memory (EPROM) has an output node with a variable resistance PMOS transistor load device interconnected between a fixed voltage potential and the output node. A gate bias for the PMOS transistor load device is delayed whereby changes in conductance of the load device is delayed in response to a change in voltage on the output node. Access time for the sense amplifier is improved by the delayed change in conductance in the load device.

Abstract: A flash EPROM cell is fabricated using a standard two polysilicon enhancement mode n-channel transistor process. An active transistor region is formed in a silicon substrate by growing a field oxide around the region. A first polysilicon layer is deposited, etched, and oxidized to form an insulated control gate electrode. A second polysilicon layer is deposited over the active transistor region and the control gate electrode and then anisotropically etched to remove all of the second polysilicon material except for a filament adjacent to the control gate electrode. The filament can be on one side of the control gate electrode or on opposing sides of the control gate electrode. Source and drain regions are formed in the active transistor region with the control gate electrode and the floating gate electrode positioned over the channel region interconnecting the source and drain regions.

Abstract: An Electrically Programmable Read Only Memory (EPROM) memory cell includes a serially connected Complementary Metal Oxide Silicon (CMOS) transistor pair having common floating gates and common control gates. A third n-type floating gate field effect transistor is utilized for programming the memory cell. The floating gate and the control gate of the third transistor are connected to the common floating gates and the common control gates, respectively, of the Complementary Metal Oxide Silicon (CMOS) transistor pair. The memory cell is tri-statable by connecting the source of the p-channel transistor of the Complementary Metal Oxide Silicon (CMOS) pair to the common control gates.

Abstract: A programmable logic device having greater design flexibility through use of a plurality of programmable macrocells in conjunction with programmable gate arrays. Each macrocell includes a programmable reconfigurable register for receiving sum terms from the array, and an input/output (I/O) terminal connected to receive an output from the programmable reconfigurable register. Two separate feedbacks from the macrocell to the gate array are provided. The first feedback has multiple inputs including the register output, and the second feedback has multiple inputs including the I/O terminal. Accordingly, the I/O terminal and the register can function independently.

Abstract: A CMOS ring oscillator includes an odd number of serially connected inverter stages with each stage comprising a CMOS transistor pair. The output of each stage is taken at the common terminal of the CMOS transistor pair with capacitive means shunting the output of each stage to circuit ground. The input of each stage is applied at the gate of the p-channel transistor. A fixed reference voltage, V.sub.REF, is applied to the gate of each n-channel transistor, whereby the discharge of voltage on the capacitive means through the n-channel transistor is independent of supply voltage.

Abstract: A programmable memory cell useful in a logic cell array draws no D.C. power in either a "1" or a "0" state. The cell includes a CMOS transistor pair including a p-channel transistor connected to a positive voltage source and an n-channel transistor connected to a circuit ground potential. The cell output is connected to a common terminal of the CMOS transistor pair. The CMOS transistor pair has a common floating gate which is selectively charged for programming the cell. In a preferred embodiment, the floating gate comprises a first polycrystalline silicon layer (polysilicon), and capacitive means including a second polysilicon layer spaced from and capacitively coupled with the first polysilicon layer is utilized to selectively applying charge to the common floating gate.

Abstract: An EEPROM or EPPROM programming switch operable at low circuit voltage (V.sub.CC) includes a first pair of native field effect transistors interconnected between a word line and a programming voltage potential and a second pair of serially connected native transistor devices connected between a charge pump node and the programming voltage. The gate electrodes of the first pair of transistors are connected to the charge pump node and the gate electrodes of the second pair of transistors are connected to the word line. Decoding means is provided for preventing charge accumulation of the word line when the word line is not selected and for permitting charge accumulation of the word line when the word line is selected for programming. The common terminals of the first and second transistors and the third and fourth transistors are connected to a bias circuit for preventing conduction of the transistors when the word line has not been selected for programming.