Abstract: A computer system is provided having a register stack engine to manage data transfers between a backing store and a register stack. The computer system includes a processor and a memory coupled to the processor through a memory channel. The processor includes a register stack to store data from one or more procedures in one or more frames, respectively. The register stack engine monitors activity on the memory channel and transfers data between selected frames of the register stack and a backing store in the memory responsive to the available bandwidth on the memory channel.

Abstract: A branch operation is processed using a branch predict instruction and an associated branch instruction. The branch predict instruction indicates a predicted direction, a target address, and an instruction address for the associated branch instruction. When the branch predict instruction is detected, the target address is stored at an entry indicated by the associated branch instruction address and a prefetch request is triggered to the target address. The branch predict instruction may also include hint information for managing the storage and use of the branch prediction information.

Abstract: A method and apparatus to handle exceptions. The method receives and prioritizes exceptions resulting from executing an instruction on different elements of an operand. The exceptions are reported to an interrupt service register which communicates the exceptions to an exception handler to effectively process the exceptions.

Abstract: A method for processing one or more branch instructions in an instruction bundle is provided. The instructions are ordered in an execution sequence within the bundle, with the branch instructions ordered last in the sequence. The bundled instructions are transferred to execution units indicated by a template field that is associated with the bundle. The first branch instruction in the bundle's execution sequence that is resolved taken is determined, and retirement of subsequent instructions in the execution sequence is suppressed.

Abstract: A processor that is configured to execute a programmed flow of instructions is disclosed. The processor includes a register stack (RS). The register stack (RS) has a portion allocated for dirty registers. The processor also includes a register stack engine (RSE) to exchange information, in one of an instruction execution dependent and independent modes, between the RS and storage area. The processor also includes a flush control circuit to generate to the RSE, dependent of instruction execution a signal, in response to which, the RSE spills to the storage area all dirty registers, from the RS. A computer implemented method in a processor is also provided. The processor includes a register stack (RS) device that includes a portion allocated for dirty registers. The portion is defined by first and second physical register numbers.

Abstract: A branch prediction instruction is provided that includes hint information for indicating a storage location for associated branch prediction information in a hierarchy of branch prediction storage structures. When the hint information is in a first state, branch prediction information is stored in a first structure that provides single cycle access to the stored information. When the hint information is in a second state, the branch prediction information is stored in a second structure that provides slower access to the stored information.

Abstract: A method for returning from an interrupting context to an interrupted context in a processor is disclosed. The processor executes a programmed flow of instructions. The processor includes a register stack (RS) and a register stack engine (RSE) to exchange information between the RS and the storage area. The method includes the following steps: (a.) A first pointer (PTR) is generated. The pointer (PTR) points to a location in the storage area where dirty registers (previously unsaved) of an interrupted context are stored; (b.) It is determined whether a mathematical relation is valid between the first pointer and the second pointer (BSPLOAD) to a location in the storage area from where the RSE is configured to load dirty register values into the RS; (c) The second pointer is caused to point to a next location in the storage area if the relation is valid; and (d) A register of the RS is loaded with a content of the next location in the storage area until the mathematical relation becomes invalid.

Abstract: A computer implemented method for switching from an interrupted context to an interrupting context in a processor is provided. The processor includes a register stack (RS) that has first and second portions. The processor includes a register stack engine (RSE) that exchanges information, in one of instruction execution dependent and independent modes between the second portion and a storage area. The method includes the following steps: a state of the RSE of the interrupted context is preserved; a COVER instruction is issued; a first (BSPSTORE) pointer is preserved. The first pointer points to a location in the storage area, of the interrupted context, where a next register of the second portion is to be written; first pointer is written with a value corresponding to the interrupting context; and a second pointer (BSP) is preserved. The new first and second pointers in the interrupting context define the storage area of RS values associated with the interrupted context.

Abstract: A computer-implemented method of switching contexts in a processor is provided. The processor includes a register stack (RS) that has first and second portions. The processor includes a register stack engine (RSE) to exchange information, in one of instruction execution dependent and independent modes between the second portion and the storage area. The computer implemented method of switching contexts includes the following steps: It is determined whether an interrupt occurred; a first register (IFM) configured to store a content of a second register (CFM) is invalidated, the CFM is configured to store control information related to the first portion; it is determined whether an interrupt handler needs to access the RS; and if so, the IFM is validated, the content of the CFM is copied to the IFM, and RSE is caused to exchange information between both the first and second portions of the RS and the storage area.

Abstract: A method and apparatus for handling branch instructions contained within a source program includes applying a set of heuristics to classify each of the branch instructions in the source program as either a hard-to-predict type or a simple type of branch. A system implements a multi-heuristic branch predictor comprising a large, relatively simple branch predictor having many entries, to accommodate the majority of branch instructions encountered in a program, and a second, relatively small, sophisticated branch predictor having a few entries. The sophisticated branch predictor predicts the target addresses of the hard-to-predict branches. By mapping hard-to-predict branches to the sophisticated branch predictor, and easy-to-predict branches to the relatively simple branch predictor, overall performance is enhanced.

Abstract: The present invention provides a method and apparatus for restoring a predicate register set. One embodiment of the invention includes decoding a first instruction which specifies a restoring operation to be performed on a predicate register set. In response to the first instruction, a mask is used to select a plurality of the predicate registers that are to be restored. The mask of the present invention consists of a first set of bits, with each bit of the first set of bits corresponding to a register in the predicate register set. When a bit of the first set of bits is set to one, the predicate register corresponding to that bit is restored. In one embodiment, the mask further includes one bit corresponding to a plurality of registers in the predicate register set, wherein when that bit is set to one, the plurality of registers corresponding to that bit are restored.