Abstract: Operating a double-sided double-base bipolar junction transistor. One example is a method of operating a switch assembly, the method comprising: blocking current flow from an upper terminal of the switch assembly to a lower terminal by a transistor; and then responsive to assertion of a conduction signal, conducting a first load current from the upper terminal to a lower terminal. The conducting the first load current may be by: closing an upper-main FET coupled between the upper terminal and an upper collector-emitter of the transistor; closing a lower-main FET coupled between a lower collector-emitter of the transistor and the lower terminal; driving a first turn-on current to an upper base of the transistor from an upper current source; and then providing a first steady-state current to the upper base from the upper current source, the first steady-state current lower than the first turn-on current.

Abstract: A hybrid switch circuit for coupling two circuit terminals together is disclosed. The hybrid switch circuit includes a set of bidirectional switch devices coupled between a first circuit terminal and a second circuit terminal. The hybrid switch circuit also includes a set of unidirectional switch devices that are also coupled between the first circuit terminal and the second circuit terminal. In some cases, the set of bidirectional switch devices may be implemented using bidirectional double-base bipolar junction transistors, while the set of unidirectional switch devices may be implemented using wide bandgap transistors. In response to a de-assertion of a switch signal, a control circuit may open the set of bidirectional switch devices and, after a period of time has elapsed, open the set of unidirectional switch devices.

Abstract: Double-sided double-base bipolar junction transistor, and methods of operation. One example is a method comprising conducting main load current from an upper terminal of a switch assembly, through a double-sided double-base bipolar junction transistor (DSDB-BJT) of the switch assembly, and then through a lower terminal of the switch assembly. The conducting may be by: injecting charge carriers into an upper drift region of the DSDB-BJT as the main load current flows into an upper collector-emitter of the DSDB-BJT; and simultaneously injecting charge carriers into a lower drift region of the DSDB-BJT as main load current flows out of a lower collector-emitter of the DSDB-BJT.

Abstract: Bi-directional trench power switches. At least one example is a semiconductor device comprising: an upper base region associated with a first side of a substrate of semiconductor material; an upper-CE trench defined on the first side, the upper-CE trench defines a proximal opening at the first side and a distal end within the substrate; an upper collector-emitter region disposed at the distal end of the upper-CE trench; a lower base region associated with a second side of substrate; and a lower collector-emitter region associated with the second side.

Abstract: Thin bidirectional bipolar junction transistor (BJT) devices and methods for fabricating thin bidirectional BJT devices. The method includes forming a first base region and a first emitter/collector region on a first side of a first thick semiconductor wafer. The method also includes removing a portion of the first thick semiconductor wafer to produce a first thin semiconductor wafer. The method further includes forming a second base region and a second emitter/collector region on a second side of the first thin semiconductor wafer opposite the first side. The method also includes producing a second thin semiconductor wafer. The method further includes bonding the first thin semiconductor wafer to the second thin semiconductor wafer.

Abstract: Operating a PNP double-sided double-base bipolar junction transistor (DSDB BJT). One example is a method of operating a DSDB-BJT, the method comprising: conducting a first load current from an upper terminal of the power module to an upper base of the transistor, through the transistor, and from a lower base to a lower terminal of the power module; and then responsive assertion of a first interrupt signal interrupting the first load current from the lower base to the lower terminal by opening a lower-main FET and commutating a first shutoff current through a lower collector-emitter of the transistor to the lower terminal; and blocking current from the upper terminal to the lower terminal by the transistor.

Abstract: The present application teaches, among other innovations, power semiconductor devices in which breakdown initiation regions, on BOTH sides of a die, are located inside the emitter/collector regions, but laterally spaced away from insulated trenches which surround the emitter/collector regions. Preferably this is part of a symmetrically-bidirectional power device of the “B-TRAN” type. In one advantageous group of embodiments (but not all), the breakdown initiation regions are defined by dopant introduction through the bottom of trench portions which lie within the emitter/collector region. In one group of embodiments (but not all), these can advantageously be separated trench portions which are not continuous with the trench(es) surrounding the emitter/collector region(s).

Abstract: Bi-directional trench power switches. At least one example is a semiconductor device comprising: an upper base region associated with a first side of a substrate of semiconductor material; an upper-CE trench defined on the first side, the upper-CE trench defines a proximal opening at the first side and a distal end within the substrate; an upper collector-emitter region disposed at the distal end of the upper-CE trench; a lower base region associated with a second side of substrate; and a lower collector-emitter region associated with the second side.

Abstract: Operating a bi-directional double-base bipolar junction transistor (B-TRAN). One example is a method comprising: conducting a first load current from an upper terminal of the power module to an upper-main lead of the transistor, through the transistor, and from a lower-main lead of the transistor to a lower terminal of the power module; and then responsive assertion of a first interrupt signal, interrupting the first load current from the lower-main lead to the lower terminal by opening a lower-main FET and commutating a first shutoff current through a lower-control lead the transistor to the lower terminal; and blocking current from the upper terminal to the lower terminal by the transistor.

Abstract: Bi-directional trench power switches. At least one example is a semiconductor device comprising: an upper base region associated with a first side of a substrate of semiconductor material; an upper-CE trench defined on the first side, the upper-CE trench defines a proximal opening at the first side and a distal end within the substrate; an upper collector-emitter region disposed at the distal end of the upper-CE trench; a lower base region associated with a second side of substrate; and a lower collector-emitter region associated with the second side.

Abstract: A double-sided cooling package for a double-sided, bi-directional junction transistor can include a double-sided, bi-directional, junction transistor chip with an individual, double-sided, bi-directional power switch (collectively, a DSTA). The DSTA can be sandwiched between heat sinks. Each heat sink can include a direct plating copper (DPC) structure, a direct copper bonding (DCB) structure or a direct aluminum bond (DAB) structure. In addition, each heat sink can have opposed first and second copper layers on a substrate, and copper contacts that extend from a respective second copper layer through vias in each substrate to an exterior of the cooling package.

Abstract: Operating a bi-directional double-base bipolar junction transistor (B-TRAN). One example is a method comprising: injecting charge carriers at a first rate into an upper base of the transistor, the injecting at the first rate results in current flow through the transistor from an upper collector-emitter to a lower collector-emitter, and the current flow results in first voltage drop measured across the upper collector-emitter and the lower collector-emitter; and then, within a predetermined period of time before the end of a first conduction period of the transistor, injecting charge carriers into the upper base at a second rate lower than the first rate, the injecting at the second rate results in second voltage drop measured across the upper collector-emitter and the lower collector-emitter, the second voltage drop higher than the first voltage drop; and then making the transistor non-conductive at the end of the conduction period.

Abstract: Layout to reduce current crowding at endpoints. At least one example is a semiconductor device comprising: an emitter region defining an inner boundary in the shape of an obround with parallel sides, and the obround having hemispherical ends each having a radius; a base region having a first end, a second end opposite the first end, and base length, the base region disposed within the obround with the base length parallel to and centered between the parallel sides, the first end spaced apart from the first hemispherical end by a first gap greater than the radius, and the second end spaced apart from the second hemispherical ends by a second gap greater than the radius.

Abstract: The present application teaches, among other innovations, power semiconductor devices in which breakdown initiation regions, on BOTH sides of a die, are located inside the emitter/collector regions, but laterally spaced away from insulated trenches which surround the emitter/collector regions. Preferably this is part of a symmetrically-bidirectional power device of the “B-TRAN” type. In one advantageous group of embodiments (but not all), the breakdown initiation regions are defined by dopant introduction through the bottom of trench portions which lie within the emitter/collector region. In one group of embodiments (but not all), these can advantageously be separated trench portions which are not continuous with the trench(es) surrounding the emitter/collector region(s).

Abstract: The present application teaches, among other innovations, power semiconductor devices in which breakdown initiation regions, on BOTH sides of a die, are located inside the emitter/collector regions, but laterally spaced away from insulated trenches which surround the emitter/collector regions. Preferably this is part of a symmetrically-bidirectional power device of the “B-TRAN” type. In one advantageous group of embodiments (but not all), the breakdown initiation regions are defined by dopant introduction through the bottom of trench portions which lie within the emitter/collector region. In one group of embodiments (but not all), these can advantageously be separated trench portions which are not continuous with the trench(es) surrounding the emitter/collector region(s).

Abstract: Methods and systems for double-sided semiconductor device fabrication. Devices having multiple leads on each surface can be fabricated using a high-temperature-resistant handle wafer and a medium-temperature-resistant handle wafer. Dopants can be introduced on both sides shortly before a single long high-temperature diffusion step diffuses all dopants to approximately equal depths on both sides. All high-temperature processing occurs with no handle wafer or with a high-temperature handle wafer attached. Once a medium-temperature handle wafer is attached, no high-temperature processing steps occur. High temperatures can be considered to be those which can result in damage to the device in the presence of aluminum-based metallizations.

Abstract: Operating a bi-directional double-base bipolar junction transistor (B-TRAN). One example is a method comprising: conducting a first load current from an upper terminal of the power module to an upper-main lead of the transistor, through the transistor, and from a lower-main lead of the transistor to a lower terminal of the power module; and then responsive assertion of a first interrupt signal, interrupting the first load current from the lower-main lead to the lower terminal by opening a lower-main FET and commutating a first shutoff current through a lower-control lead the transistor to the lower terminal; and blocking current from the upper terminal to the lower terminal by the transistor.

Abstract: Bi-directional trench power switches. At least one example is a semiconductor device comprising: an upper base region associated with a first side of a substrate of semiconductor material; an upper-CE trench defined on the first side, the upper-CE trench defines a proximal opening at the first side and a distal end within the substrate; an upper collector-emitter region disposed at the distal end of the upper-CE trench; a lower base region associated with a second side of substrate; and a lower collector-emitter region associated with the second side.

Abstract: Operating a bi-directional double-base bipolar junction transistor (B-TRAN). One example is a method comprising: conducting a first load current from an upper terminal of the power module to an upper collector-emitter of the transistor, through the transistor, and from a lower collector-emitter to a lower terminal of the power module; and then responsive assertion of a first interrupt signal, interrupting the first load current from the lower collector-emitter to the lower terminal by opening a lower-main FET and thereby commutating a first shutoff current through a lower base of the transistor to the lower terminal; and blocking current from the upper terminal to the lower terminal by the transistor.

Abstract: Current sharing among bidirectional double-base bipolar junction transistors. One example is a method comprising: conducting current through a first bidirectional double-base bipolar junction transistor (first B-TRAN); conducting current through a second B-TRAN the second B-TRAN coupled in parallel with the first B-TRAN; measuring a value indicative of conduction of the first B-TRAN, and measuring a value indicative of conduction of the second B-TRAN; and adjusting a current flow through the first B-TRAN, the adjusting responsive to the value indicative of conduction of the first B-TRAN being different than the value indicative of conduction of the second B-TRAN.