Abstract: A device for multiplying two bit sequences has a controller that selects and activates exactly one multiplier unit from a plurality of parallel multiplier units, according to a random signal. A partial multiplier unit shared by all the multiplier units receives and multiplies operands formed by the respectively activated multiplier unit. Each multiplier unit implements a different multiplication method with a respective selector unit that selects segments of the bit sequences to be multiplied, in accordance with a selection plan adapted to the respective multiplication method, to form operands from one or more segments and outputs the operands. The respective accumulation unit receives step by step partial products from the partial multiplier unit, accumulates the partial products in accordance with an accumulation plan adapted to the implemented multiplication method and matching the selection plan, and outputs the calculated product of after accumulation has been completed.

Abstract: A thermoelectric semiconductor component, comprising an electrically insulating substrate surface and a plurality of spaced-apart, alternating p-type (4) and n-type semiconductor structural elements (5) which are disposed on said surface and which are connected to each other in series in an electrically conductive manner alternatingly at two opposite ends of the respective semiconductor structural elements by conductive structures, in such a way that a temperature difference (2?T) between the opposite ends produces an electrical voltage between the conductive structures or that a voltage difference between the conductive structures (7, 9; 13, 15) produces a temperature difference (2?T) between the opposite ends, characterized in that the semiconductor structural elements have a first boundary surface between a first and a second silicon layer, the lattice structures of which are considered ideal and are rotated by an angle of rotation relative to each other about a first axis perpendicular to the substrate su

Abstract: An MEMS component including a monolithically integrated electronic component with a multi-plane conductor track layer stack which is arranged on a substrate and into which is integrated a cantilevered elastically movable metallic actuator which is arranged in the multi-plane conductor track layer stack at the level of a conductor track plane and is connected by via contacts to conductor track planes which are arranged thereabove or therebeneath and which apart from an opening in the region of the actuator are separated from the conductor track plane of the actuator by a respective intermediate plane insulator layer, wherein the actuator is formed from a metallically conductive layer or layer combination which is resistant to corrosive liquids or gases and which contains titanium nitride or consists of titanium nitride.

Abstract: A method of reducing a phase error caused by a plurality of error sources in a signal which is present in a digital frequency representation in the form of a sequence of a plurality of digital partial signals which are associated with a number of subcarriers (k) of a carrier. The following steps are performed for each partial signal: equalization of the partial signal (Y(i,k)), estimation of the phase error of the equalized partial signal (X(i,k)), and correction of the estimated phase error of the equalized partial signal. An embodiment of that method provides that the equalization step includes the elimination of an accumulation of a phase error of the partial signal, caused by a sampling frequency error, over the sequence of the partial signals, such that the accumulation is negligible.