Abstract: A portion of a logic emulation system is configured to sample logic values from the portion of the emulation system that is used to emulate the user digital logic design. These sampled values are then multiplexed by the emulation system to a logic analysis device. Typically, this is a commercially-available logic analyzer. To achieve this functionality, the emulation system is provided with a clock signal that has a higher frequency than the emulation clock signal received from the target or user system. This high speed clock signal is provided to logic analyzer as a strobe signal and controls the transfer of words of logic values from the emulation system to the logic analyzer. As a result, the number of signals that the logic analyzer can effectively sample for a cycle of the emulation clock is increased.

Abstract: A portion of a logic emulation system is configured to sample logic values from the portion of the emulation system that is used to emulate the user digital logic design. These sampled values are then multiplexed by the emulation system to a logic analysis device. Typically, this is a commercially-available logic analyzer. To achieve this functionality, the emulation system is provided with a clock signal that has a higher frequency than the emulation clock signal received from the target or user system. This high speed clock signal is provided to logic analyzer as a strobe signal and controls the transfer of words of logic values from the emulation system to the logic analyzer. As a result, the number of signals that the logic analyzer can effectively sample for a cycle of the emulation clock is increased.

Abstract: In a digital circuit, a method for avoiding a bus contention condition which results from an overlap of active phases of multiple bus drivers. The method avoids such bus contention condition by including holding amplifiers in the data bus and by turning on respective bus drivers only for durations sufficient to establish a data value on the data bus.

Abstract: A system and a method provide full visibility to each net of a design under modeling by saving states of the design during modeling and reconstructing waveforms at each net by logic evaluation using the saved states. In one embodiment, primary data input signals and memory output signals ("sample signals") are saved by a logic analyzer, and used in an emulator to generate state vectors from a state snapshot previously recorded. Data compression techniques can be applied to minimize storage requirements, and parallel evaluation of segments of waveforms can be achieved, since saved states for the entire period of interest are available for waveform reconstruction at the time of the logic evaluation.

Abstract: A method of configuring a configurable logic system, including a single or multi-FPGA network, is disclosed in which an internal clock signal is defined that has a higher frequency than timing signals the system receives from the environment in which it is operating. The frequency can be at least ten times higher than a frequency of the environmental timing signals. The logic system is configured to have a controller that coordinates operation of its logic operation in response to the internal clock signal and environmental timing signals. Specifically, the controller is a finite state machine that provides control signals to sequential logic elements such as flip-flops. The logic elements are clocked by the internal clock signal. In the past, emulation or simulation devices, for example, operated in response to timing signals from the environment. A new internal clock signal, invisible to the environment, rather than the timing signals is used to control the internal operations of the devices.

Abstract: A method for partitioning a logic circuit is provided for emulation under a virtual wires method using programmable logic devices. Because a virtual wires systems replace pin constraints by a corresponding gate constraint, partitioning for a virtual wires system applies novel constraints and algorithms. In one embodiment, partitioning is provided under a "flat mincut" approach in conjunction with a virtual wire cost constraint. In another embodiment, partitioning is provided under a "hierarchical mincut" in conjunction with a virtual wire cost constraint.

Abstract: A stimulus engine for a logic simulation system is used to interpret a stimulus language and generate test patterns as input to a logic simulator. The stimulus language allows a large test pattern set to be represented as a program. Special purpose hardware interprets this program and generates a sequence of input/output events to the logic simulator. The program interpretation is performed while the logic simulation is executing. Special purpose hardware is used to insure that the stimulus engine is able to generate the input/output events at a rate which does not slow down the logic simulator.

Abstract: Races and hazards in simulated logic designs are more easily detected if the logic simualtor is able to warn the designer of the presence of glitches. A glitch wall occur at the output of a logic device if an input condition causes the output to begin to change but the input condition is not present for sufficient time to allow the output to reach its stable state. The logic evaluator is the component of the logic simulator which is responsible for determining the output of a simulated device when the inputs to that device are known. The glitch detecting logic evaluator according to the present invention provides glitch detection by forcing the simulated device output to the undefined state when the device inputs change in a manner which does not allow the change to propagate to the output before a subsequent change occurs. The algorithms are designed for implementation in hardware for high performance logic simulation.

Abstract: Logic simulation is performed using special purpose hardware which operates in either one of two simulation modes. The machine allows detailed timing simulation where each device may be programmed with a delay time of zero, one, or multiple simulation time units. In addition, the machine supports zero and unit delay simulation in a high performance "unit delay" mode. The logic simulation function is partitioned into six sub-functions which are implemented in a single stage of a six-stage pipeline. The pipeline stages which implement the multi-unit delay time queue management may be switched to perform a different algorithm for unit delay simulation. The machine is able to perform extremely fast functional circuit testing and to perform detailed timing simulation without changing the circuit "netlist".