Abstract: A touch panel assembly structure includes a touch sensor substrate, a cover lens, a sealing frame, and a plurality of transparent elastic elements. The cover lens is facing the touch sensor substrate. The surface of the touch sensor substrate having a sensing region, and the sealing frame is disposed on the surface of the touch sensor substrate and surrounding the sensing region. The sealing frame includes a sealing colloid and a plurality of spacers mixed into the sealing colloid. The cover lens is attached to the touch sensor substrate by the sealing frame such that a gap is formed between the touch sensor substrate and the cover lens. The transparent elastic elements are disposed in the gap and arranged within the sensing region.

Abstract: A transparent touch panel includes a transparent substrate and a transparent layer disposed on the transparent substrate. The surface of the transparent substrate has an electrode region and a wiring region. The transparent layer includes at least one touch sensitive electrode and at least one conductive wiring. The at least one touch sensitive electrode is disposed in the electrode region and has a plurality of bent slits. The at least one conductive wiring is disposed in the wiring region and electrically connected to the touch sensitive electrode and has a bent shape.

Abstract: A current-to-voltage converter which is used to receive an input current and to generate an output voltage accordingly comprises a current tracking bias circuit, a current-to-voltage unit, and a voltage clamp bias circuit. The current tracking bias circuit generates a first bias according to the input current. The current-to-voltage unit receives the first bias and the input current, and generates the output voltage according to the input current, wherein the first bias determines a range of the input current, the current-to-voltage unit has a first current control device, and the first current control device changes a current conduction level thereof in response to the first bias, such that a rising or falling speed of the output voltage is enhanced. The voltage clamp bias circuit clamps voltage levels of two ends where the voltage clamp bias circuit is connected to the current-to-voltage unit.

Abstract: A current-to-voltage converter comprises a gain circuit, a flip circuit, and a chopper circuit. The gain circuit receives an input current, and amplifies the input current to generate an amplified current. The flip circuit receives the amplified current, and uses the amplified current to charge or discharge a capacitor thereof according to a charge signal and a discharge signal, so as to generate an output voltage, wherein before using the amplified current to charge or discharge the capacitor, the flip circuit resets the output voltage respectively to a charge reset voltage and a discharge reset voltage according to a charge reset signal and a discharge reset signal. When the capacitor is charged, the chopper circuit samples and holds the output voltage to generate a recovered voltage. When the capacitor is discharged, the chopper circuit samples, holds, and flips the output voltage to generate the recovered voltage.

Abstract: A panel module includes a substrate and a transparent electrode layer disposed on the substrate. The inner surface of the substrate has a plurality of touch-control segments. The transparent electrode layer of each touch-control segment has a coupling electrode, a plurality of first electrodes, and a plurality of second electrodes, wherein the coupling electrode, the first electrodes, and the second electrodes are arranged in an interval and insulting with each other. Each coupling electrode is separating the corresponding touch-control segment into a first-side region and a second-side region, wherein the first-side region and the second-side region are arranged on two opposite sides of the coupling electrode, the first electrodes are disposed on the first-side region, and the second electrodes are disposed on the second-side region. A portion of the transparent electrode layer disposed on any two adjacent touch-control segments are configured in a mirror symmetry arrangement.

Abstract: A method for backlight control includes: receiving a display synchronization signal; generating a backlight control signal according to the display synchronization signal; and driving a backlight source according to the backlight control signal. An apparatus for backlight control includes: a signal receiving circuit, for receiving a display synchronization signal; a control circuit, coupled to the signal receiving circuit, for generating a backlight control signal according to the display synchronization signal; and a driving circuit, coupled to the control circuit, for driving a backlight source according to the backlight control signal.

Abstract: The present disclosure provides a capacitive touch panel which includes a substrate, M driving electrodes and M×N sensing electrodes, wherein M driving electrodes and M×N sensing electrodes are formed on the substrate. The M driving electrodes are placed parallel to a first axis and are electrically isolated from each other. Each of the M driving electrodes has N sensing electrode regions defined thereon along a second axis, wherein each sensing electrode region has a sensing electrode disposed therein. Each sensing electrode electrically isolated from the driving electrode. The sensing electrode and the corresponding driving electrode generate mutual capacitance. The area associated with each driving electrode is larger than the overall area of the each corresponding sensing electrode.

Abstract: A voltage multiplying circuit comprising: a first capacitor, comprising a first terminal and a second terminal, wherein the first terminal of the first capacitor is selectively coupled to a first voltage or a second voltage, and the second terminal is selectively coupled to the first voltage or a fourth voltage; a second capacitor, comprising a first terminal and a second terminal, wherein the first terminal of the second capacitor is selectively coupled to the second voltage or the fourth voltage, and the second terminal of the second capacitor is selectively coupled to a third voltage or the fourth voltage; and a third capacitor, comprising a first terminal and a second terminal, wherein the first terminal of the third capacitor is selectively coupled to the second voltage or the fourth voltage, and the second terminal of the third capacitor is selectively coupled to a third voltage or the fourth voltage.

Abstract: A single-layer capacitive touch-control panel apparatus is provided. The single-layer capacitive touch-control panel apparatus includes a touch-control substrate and a touch-control chip. The touch-control substrate has M touch areas, and each touch area of the plurality of the touch areas includes an axial body and N electrodes. The axial body is electrically connected to the touch-control chip through a first conductive line. N electrodes are disposed on the axial body and are electrically connected to the touch-control chip through a plurality of second conductive lines. The touch-control chip is disposed on the touch-control substrate of single-layer, wherein MN are positive integer.

Abstract: A capacitive touch-control panel apparatus is illustrated. The capacitive touch-control panel apparatus includes a touch-control substrate and a hub circuit. The touch-control substrate has M touch areas, and each touch-control area includes an axial body and N electrodes. N electrodes are disposed corresponding to the axial body and are electrically connected to the hub circuit. One of the electrodes on each touch-control area is connected to one of the electrodes on the other touch-control area by one-to-one manner, wherein M and N are positive integer.

Abstract: The present invention provides a data accessing system and a data accessing method. The method comprises: separately storing a (N×M)-bit digital data in L banks of a data storage module; utilizing a register module of a data accessing interface module to transmit data of a bank for L times in sequence, and to receive and latch the digital data included by a bank from the data storage module when transmitting data each time, until the (N×M)-bit digital data is totally latched in the register module; and utilizing a multiplex output module of the data accessing interface module to continuously select a M-bit digital data from the (N×M)-bit digital data registered in the register module, and input the M-bit digital data to a data retrieving device via M data transmission lines.

Abstract: A capacitance difference detecting circuit includes a control circuit, for generating a control signal according to a first voltage and a second voltage; a first capacitor to be detected; a second capacitor to be detected; a first constant capacitor, having a terminal coupled to the first terminal of the first capacitor to be detected and the first input terminal; a second constant capacitor, having a terminal coupled to the first terminal of the second capacitor to be detected and the second input terminal; a voltage control unit, cooperating with the first capacitor to be detected, the second capacitor to be detected, the first constant capacitor and the second constant capacitor to control the first voltage and the second voltage. The voltage control unit is an adjustable capacitor and a capacitance value of the adjustable capacitor is controlled by the control signal.

Abstract: A memory access control apparatus includes a plurality of memory access request generating modules and an arbitrator. When one of the memory access request generating modules receives a second memory access event while a memory device is performing a first memory access operation according to a first memory access request in response to a first memory access event, the memory access request generating module outputs a second memory access request corresponding to the second memory access event to the memory device after a delay time. The arbitrator is implemented for arbitrating memory access requests respectively outputted from the memory accessing request generating modules.

Abstract: A semiconductor device of the present invention comprises: a P type semiconductor substrate, an N-well, a first P+ diffusion region, a second P+ diffusion region, a Schottky diode, a first N+ diffusion region, a second N+ diffusion region, a third P+ diffusion region, a fourth P+ diffusion region, a first insulation layer, a second insulation layer, a first parasitic bipolar junction transistor (BJT), and a second parasitic BJT. The Schottky diode is coupled to an input signal. The first N+ diffusion region and the second N+ diffusion region are coupled to a voltage source, respectively. When a voltage level of the input signal is higher than a voltage level of the voltage source, the Schottky diode conducts charges to make the first parasitic BJT and the second parasitic BJT not conducted.

Abstract: A comparator module applied to a voltage level clamping circuit which can be implemented in an integrated circuit (IC) is provided. The IC includes a parasitic diode coupled between a first voltage source and a second voltage source. The voltage level clamping circuit includes a switch module and a comparator module. The comparator module has an output terminal, a first input terminal coupled to a first voltage source, and a second input terminal coupled to a second voltage source. The comparator module includes a current source module, a first voltage level adjusting circuit module, a second voltage level adjusting circuit module, and a comparing circuit module.

Abstract: The present invention provides a level shift circuit capable of operating at low input voltage. The level shift circuit comprises: a first switch element coupled to a first output terminal, a second switch element coupled to a second output terminal, a third switch element coupled to the second output terminal and the first output terminal, a fourth switch element coupled to the first output terminal and the second output terminal, a first current source module for letting a current passing through the third switch element smaller than a current passing through the first switch element when the first switch element and the third switch element are conducted, and a second current source module for let a current passing through the fourth switch element smaller than a current passing through the second switch element when the second switch element and the fourth switch element are conducted.

Abstract: A signal level shifting circuit, including an input stage circuit and an output signal latching circuit. The input stage circuit receives an input signal, wherein a voltage level of the input signal falls within a first predetermined voltage range. The output signal latching circuit is cascoded with the input stage circuit, and includes: a latching circuit for generating an output signal according to the input signal, wherein a voltage level of the output signal falls within a second predetermined voltage range, and the second predetermined voltage range is different from the first predetermined voltage range; and an activating circuit, coupled to the latching circuit, for selectively enabling or disabling the latching circuit, wherein when a level transition appears to the input signal, the activating circuit disables the latching circuit.

Abstract: A voltage level clamping circuit which can be implemented in an integrated circuit (IC) and a high-speed comparator module, wherein the IC includes a parasitic diode coupled between a first voltage source and a second voltage source. The voltage level clamping circuit includes a switch module coupled between the first voltage source and the second voltage source and a comparator module having an output terminal coupled to the switch module, a first input terminal coupled to the first voltage source, and a second input terminal coupled to the second voltage source, for comparing a voltage level of the first voltage source with a voltage level of the second voltage source to generate an output signal, and transmitting the output signal to the switch module to control a conducting state of the switch module to selectively clamp the voltage level of the second voltage source.

Abstract: The present invention discloses a voltage level generating device. The voltage level generating device includes: a reference voltage generating module, a first circuit module, a second circuit module, and a switch module. The voltage level generating device disclosed in the present invention only requires a buffer, a voltage regulator, and a arithmetic logic unit (ALU) to attain the same function of the conventional common voltage level generating device, and thus the circuit layout area can be reduced so as to decrease the cost of the integrated circuit (IC). In addition, the voltage level generating device disclosed in the present invention also can select different output of voltage level in order to reduce the power consumption of a display device.

Abstract: The present invention relates to an oscillating apparatus. The oscillating apparatus includes a biasing circuit, a multi-vibrator, a detecting circuit, and a selecting circuit. The biasing circuit is for generating a bias signal, wherein the biasing circuit includes a connecting port for using an impedance device to control an oscillating frequency or for directly connecting to external clock source as a reference clock. The multi-vibrator coupled to the biasing circuit for generating the oscillating frequency according to the quantity of the biasing signal. The detecting circuit coupled to the connecting port for generating a detecting signal whether the connecting port is coupled to the impedance device or the external clock source. The selecting circuit includes an AND gate coupled to the multi-vibrator and the selection signal and an OR gate coupled to the AND gate and the connecting port.